A method and arrangement for performing a vector-matrix multiplication by synaptic components includes—a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and—a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The method and arrangement addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. The word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.

A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.

A multiport memory in which one of the ports is analog rather than digital is described. In one embodiment, the analog port functions as a read-only port and the digital port functions as a write only port. This allows the data in the core memory to be applied to an analog signal, while retaining a digital port having access to the core memory for rapid storage of data. One potential use of such a multiport memory is as a bridge between a digital computer and an analog computer; for example, this allows a digitally programmed two-port memory to derive a sum-of-products signal from a plurality of analog input signals, and a plurality of such multiport memories to be used in an analog neural network such as a programmable neural net implementing analog artificial intelligence (AI).

A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.

An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

In a computing-in-memory chip and a memory cell array structure, a memory cell array therein includes a plurality of memory cell sub-arrays arranged in an array. Each memory cell sub-array comprises a plurality of switch units and a plurality of memory cells arranged in an array; and first terminals of all memory cells in each column are connected to a source line, second terminals of all the memory cells are connected to a bit line, third terminals of all memory cells in each row are connected to a word line through a switch unit, a plurality of rows of memory cells are correspondingly connected to a plurality of switch units, control terminals of the plurality of switch units are connected to a local word line of the memory cell sub-array, and whether to activate the memory cell sub-array is controlled by controlling the local word line.

A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.

A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.

A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.