A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

The current document is directed to automated reinforcement-learning-based application managers that use local agents. Local agents provide finer-granularity monitoring of an application or application subcomponents and provide continued application management in the event of interruption of network traffic between an automated reinforcement-learning-based application manager and the application or application subcomponents managed by the automated reinforcement-learning-based application manager.

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

The current document is directed to automated reinforcement-learning-based application managers that use local agents. Local agents provide finer-granularity monitoring of an application or application subcomponents and provide continued application management in the event of interruption of network traffic between an automated reinforcement-learning-based application manager and the application or application subcomponents managed by the automated reinforcement-learning-based application manager.

A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

A fuzzy logic gate comprising an input node configured to receive an analogue input signal. A complementary metal oxide semiconductor (CMOS) logic gate is connected to the input node. A tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to an output node. The output node is configured to output an analogue output signal.

A fuzzy logic gate comprising an input node configured to receive an analogue input signal. A complementary metal oxide semiconductor (CMOS) logic gate is connected to the input node. A tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to an output node. The output node is configured to output an analogue output signal.