The present disclosure relates to a data driving device, a data processing device, and a system for driving a display device and, more particularly, it relates to a data driving device, a data processing device, and a system for smoothly performing a low-speed communication through a communication line including an alternating current coupling capacitor.

A display driving circuit includes a clock signal generator which generates a clock signal at a frequency in response to a frequency control signal, a frequency variation determiner which adaptively changes a frequency variation of the clock signal, based on a magnitude of a deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal supplied from the outside, and a frequency controller which generates the frequency control signal which updates the frequency of the clock signal, based on the frequency variation, and provides the frequency control signal to the clock signal generator.

The present disclosure relates to a microcontroller, a readout integrated circuit and a method of driving a circuit, and more particularly, to a microcontroller, a readout integrated circuit and a method of driving a circuit to transmit command signals by using a pair of lines, through which signals are transmitted from the microcontroller which is a master circuit to the readout integrated circuit which is a slave circuit, as two single-ended signal transmission lines and to control power of the readout integrated circuit which is a slave circuit.

A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.

An embodiment of the present disclosure provides a data transmission method that transmits data in a clock-embedded manner, including: dividing the data into a plurality of data packets having a bit number of ‘a’; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bits ([a−1:1]) among the data packets; converting the plurality of data packets into transition ensuring data packets by using the transition code; and transmitting the transition code and the transition ensuring data packets.

A transmission configuration and/or configuration errors and recovery may be determined or implemented by temporal interpretation of one or more signals. A transmitter may interpret one or more signals a first way during one or more time windows and a second way during one or more other time windows. Video resolution may be indicated in a V-by-One® interface by temporal interpretation of HPD and/or CDR lock. Transmission format may be indicated before or after transmission begins. Transmitter configuration error detection and recovery may be implemented by temporal interpretation. A transmitter may transmit data in an assumed/default format. A receiver may indicate the assumed transmission format is incompatible with the receiver configuration. A receiver may indicate a compatible transmission format, for example, based on timing or pulsing transitions in a temporally repurposed signal. A transmitter may respond to the repurposed signal indication by transmitting a different (e.g., compatible) format.

A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

A method of seamlessly switching over between the command mode and the video mode includes receiving a command for switching over from the command mode to the video mode; generating a sampling value by measuring a time interval between a point in time of an internal synchronization signal used in the command mode and a point in time of an external synchronization signal received in the video mode; generating a parameter for shifting the internal synchronization signal based on the sampling value; shifting the internal synchronization signal to synchronize with the external synchronization signal based on the parameter; and switching over from the command mode to the video mode when the internal synchronization signal of the command mode synchronizes with the external synchronization signal. According to the disclosure, while driving a display.

The present disclosure relates to a data driving device, a data processing device, and a system for driving a display device and, more particularly, relates to a data driving device, a data processing device, and a system for automatically optimizing the configuration of the equalizer of the data driving device in the display device.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.