An apparatus comprising a display in which a plurality of pixels are arranged in an array, and a generator configured to, in a first frame, generate first data corresponding to a first region of the display to display a first image in the first region of the display and, in a second frame, generate second data corresponding to a second region of the display, which includes the first region and is larger than the first region, to display a second image in the second region of the display is provided. A region of the second region is defined as a third region, a resolution of the first image and a resolution of at least the third region in the second image are different from each other.

Disclosed are a vector diagram generation method and apparatus, and a storage medium, the method being used in an FPGA. The method comprises: acquiring video data of an ultra-high definition video system; on the basis of the video data, generating vector diagram data; acquiring a pre-generated background image of the vector diagram; and, on the basis of the background image and the vector diagram data, generating a vector diagram. The vector diagram generation method and apparatus and storage medium provided in the present disclosure can better implement vector diagram generation of the ultra-high definition video system. (FIG. 1)

The present disclosure provides an image data processing device, an image data processing method and a display device. The image data processing device includes: a plurality of writing controllers corresponding to a plurality of image blocks into which an input image is divided, and each configured to obtain input data of one image block in each input image, determine a frame address of the input data stored in a memory, and transmit the input data to the memory in accordance with the determined frame address; and a plurality of reading controllers, each reading controller corresponding to one image block into which an output image is divided, and configured to determine a frame address of the output data of one image block in ach output image in the memory, and read output data from the memory in accordance with the determined frame address.

The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate regional processing of images for under-display device displays. Aspects of the present disclosure can identify a subsection of a set of frame layers, the identified subsection corresponding to a lower pixel density region, relative to at least one other region, of a display. Aspects of the present disclosure can also blend first pixel data for each frame layer corresponding to the identified subsection to generate second pixel data. Further, aspects of the present disclosure can populate a buffer layer based on the second pixel data. Additionally, aspects of the present disclosure can blend pixel data from the set of frame layers and the buffer layers to generate a blended image. Aspects of the present disclosure can also transmit the blended image for presentment via the display.

A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

A system and method runs a query using a GPU and generates a visualization of the query using the same GPU.

A display driving circuit includes a frame rate extractor configured to receive a vertical synchronization signal indicating a start of a k-th frame, k-th frame data including information about the k-th frame, and a data enable signal indicating an active period of the k-th frame and a variable blank period that occurs after the active period, and extract a frame rate of the k-th frame, based on the vertical synchronization signal; and an image corrector configured to correct frame data received after reception of the k-th frame data, based on the frame rate of the k-th frame, and output the corrected frame data as output image data, wherein the vertical synchronization signal is received before a start time point of the active period

A display driving circuit includes a frame rate extractor configured to receive a vertical synchronization signal indicating a start of a k-th frame, k-th frame data including information about the k-th frame, and a data enable signal indicating an active period of the k-th frame and a variable blank period that occurs after the active period, and extract a frame rate of the k-th frame, based on the vertical synchronization signal; and an image corrector configured to correct frame data received after reception of the k-th frame data, based on the frame rate of the k-th frame, and output the corrected frame data as output image data, wherein the vertical synchronization signal is received before a start time point of the active period

This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.