A system for encoding and decoding a frame (also file), such as a video, graphic, media, or other frame or data, representing a real-time graphic output from a frame buffer, output by a video camera, or another file or data. The file includes frames each comprising macroblocks. Reference frame buffers (PFTs), virtual frame buffer tables (VFTBs) of equal number to the PFTs, each VFTB corresponds to a respective PFT, and respective sectors of each PFT for respective macroblocks are created. Frames of the file are encoded/decoded by successive encode/decode of macroblocks. A pointer is created in the VFBT associated with the PFT rather than encoding/decoding any matching macroblock. The pointer and its reference are relied on for each already encoded/decoded macroblock retained in the PFT. Processing, memory, bandwidth and power requirements for encoding or decoding are reduced.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

A rendering method is provided. The method includes: initializing a surface flinger to establish at least two buffer memories; confirming correspondence between all visible surfaces and the at least two buffer memories, rendering all of the visible surfaces to the corresponding buffer memories according to the correspondence, and combining all of the buffer memories to output a result for display; determining whether a change occurs in the visible surfaces; when the change occurs in the visible surfaces, identifying the buffer memory where the visible surface with the change is located; rendering again the visible surfaces that need to be rendered in the identified buffer memory, and combining the buffer memory that is rendered again with the buffer memory that is not rendered again to output a result for display.

A processing system reduces latency and improves predictability of a scan out position to support graphics processing unit (GPU) front buffer rendering with a variable refresh rate (VRR) display. The GPU detects whether front buffer rendering such as inking is occurring on a frame-by-frame basis. In order to maintain a safe distance from the current scan out position and achieve low latency to improve the user experience, the GPU increases the refresh rate of the VRR display to a low-latency (high-frequency) fixed refresh rate in response to detecting front buffer rendering. In some embodiments, the GPU decreases the refresh rate in response to detecting a static screen to save power.

A system and method for sharing information amongst user display devices, such as cell phones, smart phones, tablet computers, or other devices with an electronically controllable screen or display, in a peer to peer (P2P) network, to display one image or video across the totality of all of the display devices, regardless of where the display devices are positioned or how they are oriented relative to each other, and a system and method for identifying the exact position and orientation of each display device.

Embodiments disclosed herein relate to device and method for processing frames. For example, a buffer of a device is arranged to store a plurality of rendered frames rendered at a frame rendering rate and a time stamp for each of rendered frames. A compositor of a device is arranged to obtain a timestamp of a synchronisation signal for synchronising the display of frames with a display refresh rate. In response to obtaining a timestamp of a synchronisation signal, a compositor is arranged to trigger access to a buffer to obtain two rendered frames having timestamps closest to a timestamp of a synchronisation signal. An interpolator of a device is arranged to generate an interpolated rendered frame for display by performing an interpolation operation using two rendered frames. An interpolation operation takes into account the difference between timestamps of each of two rendered frames and a timestamp of a synchronisation signal.

Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

The invention provides an image output device coupled to a first and second signal source and a method thereof. The image output device includes memories configured to store frame image data respectively, a source selection circuit coupled to the first and second signal sources and the memories and configured to choose to store a first frame image data transmitted by the first or second signal source in one of the memories according to a working state of the first signal source, and an image output circuit coupled to the memories and the source selection circuit and configured to output the first frame image data stored in one of the memories. The image output device may rapidly switch to a backup signal source when the signal source is unstable to achieve fast switching and perfect connection.