Patent classifications
G09G2300/0408
Circular display device with narrow bezel and driving method thereof
Provided is a display device having the following structure and driving method thereof. The display device comprises a circular display panel including an active area on which an image is displayed and a non-active area on which no image is displayed, a gate driving circuit disposed in the non-active area to drive a plurality of gate lines, a first data driving circuit disposed in the non-active area to drive first-group data lines in the circular display panel, and a second data driving circuit disposed in the non-active area, in a position opposite to the first data driving circuit with respect to the active area, to drive second-group data lines in the circular display panel. The frequency of a data clock is reduced using a plurality of data driving circuits in a pad area. The bezel size of a circular display panel is reduced.
Display panel and display device including the same
A display panel includes: a plurality of divided driving parts, wherein at least a divided driving part of the divided driving parts includes: a first connection line extending in a first direction; a second connecting line extending in the first direction and spaced apart from the first connection line in a second direction crossing the first direction; a first gate line extending in the second direction and electrically connected to the first connection line; a second gate line extending in the second direction, being spaced apart from the first gate line, and being electrically connected to the second connection line; a first pixel in a first pixel column and a first pixel row and electrically connected to the first gate line; and a second pixel in the first pixel column and a second pixel row and electrically connected to the second gate line.
Display device including block patterns
A display device includes a substrate on which an active region and a non-active region disposed are defined. The non-active region at least partially surrounds the active region. A light-emitting element is disposed in the active region on the substrate. An encapsulation layer is disposed on the light-emitting element. Block patterns are disposed in the non-active region on the substrate and at least partially surround the active region. The non-active region includes a first non-active region positioned at a first side of the active region and a second non-active region positioned at a second side of the active region. There are more block patterns disposed in the first non-active region than in the second non-active region.
ARRAY SUBSTRATE AND FABRICATION METHOD THEREFOR, SHIFT REGISTER UNIT, AND DISPLAY PANEL
Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.
DISPLAY PANEL, DETECTION METHOD THEREOF AND DISPLAY DEVICE
Provided are a display panel, a detection method thereof and a display device. A scan driving circuit, signal pins and a first gating circuit are disposed in the display panel. Signal pins include a detection signal pin and an enable signal pin. The scan driving circuit includes scan drive units disposed in a cascade manner. The first gating circuit includes a first switch unit and a second switch unit. An input terminal of the first switch unit is electrically connected to a scan signal detection terminal of an Nth-stage scan drive unit. An input terminal of the second switch unit is electrically connected to a scan signal detection terminal of a first-stage scan drive unit. An output terminal of the first switch unit and an output terminal of the second switch unit are both electrically connected to the detection signal pin. The first switch unit is configured to turn on in a forward scan detection stage and turn off in a backward scan detection stage. The second switch unit is configured to turn on in the backward scan detection stage and turn off in the backward scan detection stage.
DISPLAY APPARATUS AND MULTI-SCREEN DISPLAY APPARATUS INCLUDING THE SAME
Discussed is a display apparatus including a substrate including a display portion, a plurality of pixels connected to a gate line and a data line disposed in the display portion, and a gate driving circuit disposed in the display portion to drive the gate line. The gate driving circuit includes a stage circuit unit including a plurality of stage circuits respectively disposed in a plurality of division regions defined in the display portion, and a circuit repair portion configured to repair at least one of the plurality of stage circuits and including a plurality of repair patterns. Further, at least one of the plurality of repair patterns is configured to be electrically disconnected from the at least one of the plurality of stage circuits.
DISPLAYS WITH DUAL-PIXEL DRIVERS
A dual-pixel-driver display includes pixels distributed in an array of rows and columns defining a display area and a dual-pixel driver disposed within the display area. Ones of the pixels are grouped in mutually exclusive first and second pixel clusters. The dual-pixel driver comprises a driver input, a first driver output, and a second driver output. The first driver output and the second driver output are both commonly responsive to the driver input. The first driver output drives the pixels in the first pixel cluster and the second driver output drives the pixels in the second pixel cluster.
Electro-optical module, power supply substrate, wiring substrate, and electronic apparatus
This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced. The electro-optical module includes a first connecting portion connecting a first end of the flexible substrate to a display panel and configured to receive a signal from the driver, and a second connecting portion connecting the first end of the flexible substrate to the display panel and configured to receive the driving voltage from a third connecting portion at a second end of the flexible substrate.
Emission control method for driver circuit of display panel
A first driver circuit is configured to cooperate with a second driver circuit to control a display panel, wherein the first driver circuit is configured to output display data to a first area of the display panel and the second driver circuit is configured to output display data to a second area of the display panel. A method used for the first driver circuit includes outputting at least one emission control signal to control the second area of the display panel when the second driver circuit is disabled.
OPERATIONAL AMPLIFIER CIRCUIT AND OPERATIONAL AMPLIFIER COMPENSATION CIRCUIT FOR AMPLIFYING INPUT SIGNAL AT HIGH SLEW RATE
An operational amplifier compensation circuit includes; a first transistor activated/deactivated in response to a signal level difference between an input signal applied to an operational amplifier and an output signal provided by the operational amplifier, a first signal amplifying circuit including a second transistor and a first load, wherein the first signal amplifying circuit is configured to generate a first gate voltage amplified in response to the voltage level difference between the input signal and the output signal in relation to an internal resistance of the second transistor and a resistance of the first load when the first transistor is activated, and a third transistor configured to generate a first compensation current in response to the amplified first gate voltage and provide the first compensation current to the operational amplifier.