A light emitting substrate, a method of driving a light emitting substrate, and a display device are provided. The light emitting substrate includes a plurality of light emitting units arranged in an array. Each light emitting unit includes a driving circuit, a plurality of light emitting elements, and a driving voltage terminal. The plurality of light emitting elements are sequentially connected in series and connected between the driving voltage terminal and the output terminal of the driving circuit. The driving circuit is configured to output a relay signal through the output terminal in a first period according to a first input signal received by the first input terminal and a second input signal received by the second input terminal, and supply a driving signal to the plurality of light emitting elements sequentially connected in series through the output terminal in a second period.

A display device includes a display panel including data lines configured to receive an image signal, gate lines configured to receive a scan signal, and gate connection lines configured to transmit the scan signal to the gate lines; and a multi-chip film package including, on a film, a first gate integrated circuit (IC) configured to transmit a first scan signal to the gate connection lines through first gate output lines, a second gate IC configured to transmit a second scan signal to the gate connection lines through second gate output lines, and a source IC configured to transmit the image signal to the data lines through source output lines. Each of the first gate output lines is between two adjacent source output lines, and each of the second gate output lines is between two adjacent source output lines.

A light emitting display apparatus includes a gate driver including stages provided in a substrate and a plurality of gate lines connected to the stages. Each of the stages includes a shift register and two buffers connected to the shift register, a first buffer of two buffers configuring an n.sup.th stage and a first shift register configuring the n.sup.th stage are provided in an n.sup.th horizontal portion and a second buffer of the two buffers is provided in an n+2.sup.th horizontal portion, a third buffer of two buffers configuring an n+1.sup.th stage and a second shift register configuring the n+1.sup.th stage are provided in an n+3.sup.th horizontal portion and a fourth buffer of the two buffers is provided in an n+1.sup.th horizontal portion, and the n.sup.th horizontal portion is a region including pixels which are arranged along a 4n−3.sup.th gate line and a 4n−2.sup.th gate line.

A display apparatus comprises a substrate including a display area and a non-display area adjacent to the display area, a plurality of pixels disposed in the display area, a gate driver disposed on both sides of the display area in the non-display area, the gate driver comprising a plurality of stages including a first stage and a second stage, and a plurality of gate lines extending from the gate driver to the display area, wherein the plurality of gate lines include a first gate line including a linear portion and coupled to the first stage, and a second gate line including a linear portion and a curved portion and coupled to the second stage, and wherein a size of the second stage may be larger than a size of the first stage.

An electronic device including a substrate, a plurality of first signal lines, and a plurality of second signal lines is provided. The first signal lines are disposed on the substrate. Each of the first signal lines includes a first intersecting section and a first extending section. The first intersecting section each has a constant extending direction. The first intersecting section is connected to the first extending section, while the first intersecting section and the first extending section have different extending directions. The second signal lines are disposed on the substrate. Each of the second signal lines includes a second intersecting section. The second intersecting section each has a constant extending direction. The second signal lines intersect with the first signal lines to form a plurality of intersections on each of the first signal lines, and the intersections are located on the first intersecting sections.

The present application provides a display panel. The display panel includes: gate driver on array (GOA) units arranged along a first direction; clock signal lines arranged along a second direction and arranged at one side of the GOA units; the connection lines, each of the connection lines being extended along the second direction and connected between the corresponding clock signal line and the corresponding GOA units; and a first electrode arranged at one side of the GOA units, the clock signal lines, and the connection lines. The first electrode includes an opening, and the opening is arranged corresponding to at least one of the clock signal lines and/or at least one of the connection lines.

A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.

A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

A display panel including a display region including first and second display regions, and sub-pixels in the display region, data lines electrically connected to the sub-pixels and including first data lines in the first display region and second data lines located in the second display region; a shift register in the first display region and including cascaded shift units, each shift unit being divided into at least two sub-units, and one sub-unit being located at a side of one sub-pixel connecting lines electrically connected to the sub-units of the shift units, one of the first data lines overlapping with one of the connecting lines in a direction perpendicular to a plane of the display panel; and compensation structures located in the second display region, and each overlapping with at least one of the second data lines in the direction.

A display device includes pixels electrically connected to a plurality of scan lines and a plurality of data lines, respectively, a scan driver that provides a scan signal to each of the plurality of scan lines, a voltage supply that supplies a first gate voltage to the scan driver through a first gate power line, and a voltage compensator. The voltage compensator senses a partial voltage of the first gate voltage applied to the scan driver through a feedback line. The voltage compensator compensates the first gate voltage with a second gate voltage in case that the sensed first gate voltage is greater than a first reference voltage.