Disclosed is a display panel including a base substrate (101), and a gate drive circuit (40), a plurality of clock signal lines, and a plurality of connecting lines (51) that are disposed on the base substrate (101). The plurality of clock signal lines are located on a side of the gate drive circuit (40) along a first direction (X) and are arranged in sequence. Each connecting line (51) is electrically connected with the gate drive circuit (40) and a clock signal line. At least one connecting line (51) includes a load adjusting portion (512) configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion (512) of the at least one connecting line (51) on the base substrate (101) is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate (101).

A display panel includes a first substrate having a display area and a peripheral area. The display area includes pixels with first output wires connected to the pixels. A first driver is connected to the first output wires and positioned in the peripheral area at a first side of the display area. The first substrate includes a notch portion having a curved edge and the display area has a first display portion and a second display portion with the notch portion therebetween. At least one of the first output wires is a first main line at the first display portion, a second main line at the second display portion, and a first connecting line that is connected to the first main line and the second main line and is at the peripheral area between the first display portion and the second display portion.

A screen includes a screen pixel array, row and column lines, a display driver integrated circuit (DDIC) circuit, a gate driver on array (GOA) circuit, a switch circuit, and an enabling signal circuit. The DDIC circuit is disposed on a side of a screen of the electronic device, and includes output channels. Each output channel is connected to two switches, each switch is connected to one row line, the GOA circuit is connected to a column line, the enabling signal circuit is connected to the switch circuit, and the screen pixel array is connected to the row and column line. The enabling signal circuit generates an enabling signal for the switch circuit. The DDIC circuit sends to-be-displayed data to the switch circuit. The switch circuit controls the two switches to alternately operate. The GOA circuit strobes a column of pixels in the screen pixel array which displays the to-be-displayed data.

A display apparatus includes: a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be provided to the pixels; k number of clock wirings to provide k number of clock signals to the plurality of stages; and k number of clock bar wirings to provide k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. The k number of clock wirings and the k number of clock bar wirings are arranged in a first order, and the k number of clock pads and the k number of clock bar pads are arranged in a second order different from the first order.

A driving circuit that includes a timing controller, a selecting module connected to the timing controller, and a level shifter connected to the selecting module, wherein the timing controller includes N pins, each of the pins provides a clock signal, and N is a positive integer; the selecting module includes N selecting units, an input terminal of each of the selecting units is connected to a corresponding pin of the timing controller, output terminals of each of the selecting units are connected to M input pins of the level shifter, and M is greater than or equal to 2. The driving circuit according to the present invention individually passes clock signals of a timing controller through selecting units and outputs to a level shifter, and pins of the timing controller can be substantially saved.

A thin film transistor structure, a gate driver on array (GOA) circuit and a display device are provided. The thin film transistor structure defines a plurality of thin film transistors by patterning an active layer. Therefore, when a defect appears in the gate insulating layer of one of the plurality of thin film transistors and a leakage path is formed, other thin film transistors will not be affected. Therefore, a problem of functional failure of a whole thin film transistor structure can be avoided.

A display panel includes an array of pixels extending in a plane and arranged in rows, wherein a first plurality of the rows extend to an edge of the pixel array and one or more rows at a corner of the pixel array are recessed from the edge. The display panel includes driver circuits each connected to a corresponding row of the pixel array and occupying an area in the plane, the area having a long dimension and an orthogonal short dimension. A first set of driver circuits are connected to corresponding rows of the first plurality of rows and a second set of driver circuits are connected to corresponding rows at the corner of the pixel array. The long dimension of each of the drivers of the first set of drivers is greater than the long dimension of each of the drivers of the second set of drivers.

The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.

A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

A driving method and driving circuit of a display panel, and a display apparatus are disclosed. The driving method includes: at a first display frequency and within a frame of scanning time, loading different first clock signals for 4N number of clock signal lines respectively, and controlling a plurality of shift registers in a gate driving circuit to work in sequence to cause the shift registers output different signals to drive gate lines row by row; and at a second display frequency and within a frame of scanning time, loading the same second clock signal for each clock signal line electrically connected to the same unit group, loading different second clock signals for clock signal lines that are electrically connected to different unit groups, and controlling the unit groups to work in sequence.