A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

A display device includes a display pixel circuit including a display light-emitting element, a reference light-emitting element, and a display driving circuit. The display pixel circuit is configured to control light emission of the display light-emitting element based on a data signal in accordance with video data. The reference light-emitting element is precluded from the control in accordance with video data. The display driving circuit is configured to acquire a reference signal indicating a current-voltage characteristic of the reference light-emitting element, acquire a characteristic signal indicating the current-voltage characteristic of the display light-emitting element, and generate a signal indicating a degree of deterioration of the display light-emitting element based on a difference of the characteristic signal from the reference signal.

A display substrate and a display apparatus. In the display substrate, at least one of the inter-opening region, the first opening peripheral region and the second opening peripheral region includes a virtual sub-pixel; the display region surrounds these three regions; the first signal line passes through the inter-opening region, provides a display signal to the pixel array and passes through the virtual sub-pixel the virtual pixel circuit of the virtual sub-pixel includes a compensation capacitor. The first electrode plate of the compensation capacitor is in the same layer as the first signal line and electrically connected with the first signal line; the second electrode plate of the compensation capacitor is in a different layer from and at least partially overlaps with the first electrode plate.

A method of fabricating an array substrate is provided. The method includes providing a substrate including a gate pad configured to bond a gate driving integrated circuit, a data pad configured to bond a data driving integrated circuit, and a plurality of peripheral layout gate (PLG) proto-lines connecting the gate pad and the data pad; forming a PLG testing pad on the substrate; forming a shorting bar connecting the PLG testing pad to first terminals of the plurality of PLG proto-lines; forming a plurality of testing pins respectively connected to second terminals of the plurality of PLG proto-lines, wherein the plurality of testing pins are formed in a first dummy region of the substrate, the first dummy region is adjacent to an array substrate region of the substrate; and connecting the plurality of testing pins to a probe unit to test connectivity of the plurality of PLG proto-lines.

Provided is a display panel including a base substrate including a first display region and a second display region, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of first light-emitting elements, and a plurality of second light-emitting elements disposed in the second display region; wherein at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements, an orthographic projection of the at least one first pixel circuit on the base substrate is at least partially overlapped with an orthographic projection of the at least one first light-emitting element on the base substrate, and at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements by a conductive trace.

The present disclosure discloses a display panel and a display apparatus. The display panel includes a display region and a non-display region surrounding the display region. The display region includes: a plurality of sub-pixels disposed in an array, and each sub-pixel includes a pixel circuit and a light emitting device. A control terminal of anode reset transistor is electrically connected with a control terminal of reset transistors in the next row of sub-pixels. The non-display region includes: a row of dummy sub-pixels, the dummy sub-pixels correspond to columns of sub-pixels in one to one correspondence, each dummy sub-pixel includes a dummy pixel circuit and a dummy light emitting device, and the dummy light emitting device does not emit light. and a control terminal of the dummy anode reset transistor is electrically connected with a control terminal of reset transistor in a first row of sub-pixels correspondingly.

The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate provided by the present disclosure has a display area and a peripheral area surrounding the display area, and includes a substrate; a plurality of pixel circuits on the substrate and in the display area; and a plurality of dummy pixel circuits on the substrate and in the peripheral area; wherein the number of transistors in each dummy pixel circuit is smaller than the number of transistors in each pixel circuit. Because the number of the transistors in the dummy pixel circuit is smaller than the number of the transistors in the pixel circuit, space occupied by the dummy pixel circuit in the peripheral area can be reduced, thereby facilitating realization of a display device with a narrow bezel.

A display panel has a display area including a light-transmitting region, at least one first region and a second region. The display panel includes sub-pixels disposed in the first region and the second region, second light-emitting devices disposed in the light-transmitting region, data lines and first transistors. The data lines include first and second data lines. A first data line is electrically connected to pixel driving circuits in a column of sub-pixels including at least one dummy sub-pixel, and a second data line is electrically connected to pixel driving circuits in a column of sub-pixels located in a same column as a column of second light-emitting devices. A second light-emitting device in the column of second light-emitting devices is electrically connected to a pixel driving circuit connected to the first data line. The first data line is electrically connected to the second data line through a first transistor.

A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

Embodiments of this disclosure disclose a display panel and a display device including the display panel. The display panel includes a base substrate, the base substrate including a display area and a non-display area around the display area, a touch electrode layer on the base substrate, the touch electrode layer being within the display area of the base substrate, and a plurality of signal lines electrically connected with the touch electrode layer, the plurality of signal lines being distributed within a first area of the non-display area adjacent to the display area. The display panel further includes a plurality of outer dummy traces within a second area of the non-display area, the second area is between the first area and an outer border of the non-display area, and the plurality of outer dummy traces and the plurality of signal lines are separated from each other.