A display device includes a display layer including a plurality of light-emitting devices and a plurality of switching devices in a one-to-one correspondence with the light-emitting devices, the plurality of light-emitting devices and the plurality of switching devices forming a monolithic structure, and a driving layer, wherein the plurality of light-emitting devices and the plurality of switching devices corresponding to the plurality of light-emitting devices are grouped into pixels and then arranged in the display layer, and the driving layer includes a plurality of driving devices configured to apply at least one driving signal to the display layer.

The present application discloses a driving structure for display panel, which comprises at least one driving group and at least one control circuit. The driving group is disposed on a display panel. Each of the driving group includes a plurality of drivers. The drivers are coupled to each other in serial. Each of the drivers is coupled to at least one display component of the display panel. The control circuit is disposed on the display panel, coupled to the driving group, and controls the driving group. The driving structure according to the present application is applied to the display panel, that requires no scan lines disposed on the display panel for reducing the complex of the structure of the display panel.

A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.

In a display device, transistors are disposed on a display panel. When the display panel has a short-circuit, the timing controller sends a signal to the level shifter to disconnect the transistors, causing the display panel to no longer receive scanning signals transmitted from GOA circuits, causing the display panel enter an overcurrent protection state, and thus preventing GOA wirings in the display panel from burning out in an event of the short-circuit.

An electronic device is provided. The electronic device includes a plurality of units. at least one of the plurality of units includes a driving circuit and a working element. The working element is coupled to the driving circuit, and driven by the driving circuit. The driving circuit receives a first data signal and a second data signal during a scan period.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

The present disclosure relates to a display device, a pixel driving circuit and a driving method thereof. The OLED pixel driving circuit includes an electroluminescent devices, first to seventh switching elements and a storage capacitor. The sixth switching element has a first terminal coupled to a first node and a second terminal coupled to a third node, the seventh switching element has a first terminal receiving an initialization voltage, and a second terminal coupled to the first node.