A display device according to an embodiment of the inventive concept includes a data driving unit, a gate driving unit, a signal control unit for controlling driving of the data driving unit and the gate driving unit, and a display panel. The data driving unit generates an internal clock signal for outputting data voltages corresponding to image data, and the display panel displays an image corresponding to the data voltages in response to a gate driving signal outputted from the gate driving unit. The data driving unit includes a filtering unit for converting a first frequency control signal received from the signal control unit so as to generate a second frequency control signal, and a clock training unit for training a clock signal received from the signal control unit so as to generate the internal clock signal in response to the second frequency control signal.

The present disclosure discloses a gate driver, a display apparatus and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver. The gate driver according to the present disclosure comprises multiple groups of driving units, each group of driving units comprising N driving units each of which comprises a shift register and a logic circuit, wherein N is an integer larger than 1, and an output of a shift register is connected to a logic circuit in each driving unit. The shift registers multiplex multiple clock signals with different timings. Each of the shift registers outputs an output signal to a corresponding logic circuit. A part of a clock signal is selected by the logic circuit for output. In this way, a function of outputting a multi-pulse waveform by the gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel.

One inventive aspect is an array substrate, which includes a plurality of touch leads, a common electrode layer, and a drive circuit. The common electrode layer is divided into a plurality of columns of self-capacitive electrodes, which are electronically connected to the drive circuit through the touch leads. The array substrate also includes a plurality of pixel units. Each touch lead is electronically connected to the self-capacitive electrode corresponding to the touch lead via a first via hole. At least one touch lead is parallel to and cross over one column of the self-capacitive electrodes. In a direction perpendicular to the array substrate, a projection of the self-capacitive electrode covers projections of a plurality of pixel units. In addition, along a direction of the touch leads, an interval between two adjacent first via holes is greater than or equal to a length of two pixel units.

A display device includes: a plurality of pixel blocks each including a plurality of pixels; a scan driver supplying a scan signal to the scan lines and to supply a control signal to the control lines; a data driver supplying an image data voltage or a low grayscale data voltage to the data lines; and a power supply supplying a reference voltage to the pixels, wherein the pixels are configured to receive the image data voltage during a first scan period of a frame, and to receive the low grayscale data voltage during a second scan period of the frame, and the reference voltage supplied to a first pixel row of at least one of the pixel blocks in the first scan period is different from the reference voltage supplied to a last pixel row of at least one of the pixel blocks in the first scan period.

An organic light emitting display device includes: pixels at crossing regions of scan lines and data lines; i (i is a natural number of 2 or more) blocks divided such that each of the blocks includes two or more scan lines; a control driver configured to supply a first control signal to i first control lines coupled, respectively, to the i blocks, and to supply a second control signal to i second control lines coupled, respectively, to the i blocks; a scan driver configured to supply a scan signal to the scan lines; and a data driver configured to supply a data signal to the data lines, wherein the scan driver is configured to supply the scan signals on a block-by-block basis, a sequence of supplying the scan signals being supplied alternately in a first direction and a second direction that is different from the first direction.

A display panel module, organic light-emitting diode (OLED) display and method of driving the same are disclosed. In one aspect, the module includes a display panel divided into a first portion and a second portion and a plurality of scan and data lines divided into groups arranged in the first and second potions. The module further includes a first scan driver configured to sequentially apply scan signals to each of the first and second scan line groups. The first scan driver is further configured to substantially simultaneously apply the scan signals to corresponding scan lines of the first and second scan line groups. The module also includes a first data driver configured to output first data voltages to the first data line group and a second data driver configured to output second data voltages to the second data line group with the same timing as the first data driver.

A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.

According to an aspect, a display apparatus includes: a plurality of pixels formed on a substrate; a plurality of semiconductor apparatuses, each of which is coupled to a part of the pixels, the part being different for each semiconductor apparatus; and wiring that couples the semiconductor apparatuses to one another. Each semiconductor apparatus includes a drive signal output circuit configured to output a drive signal to the part of the pixels, and an output controller configured to: output and receive, to and from other semiconductor apparatuses, a drive communication signal including a drive start communication signal indicating reception of a drive start signal to start driving the pixels via the wiring; and cause the drive signal output circuit to output the drive signal when determining that all the semiconductor apparatuses have received the drive start signals in accordance with the drive start communication signal.

An LED panel has an interleaved topology in which two adjacent LED rows in the LED panel are driven by different drivers. A delay time can be implemented between starting times two adjacent LED rows. Such an LCD panel can be employed to backlight an LCD panel in an LCD display. Implementing a delay time in driving the LED panel can reduce visual artifacts in the LCD display.

OR-function illumination in phased bitplanes in a high dynamic range projector is provided, which can be used to reduce flicker artifacts. The projector comprises: a light source; a premod display; a prime display, the premod display configured to modulate light from the light source to illuminate the prime display; and, a computing device. The computing device drives the prime display according to a phased sequence to transition the prime display from a leading bitplane to a following bitplane. The computing device is further configured to, at least in a time period corresponding to the prime display being driven according to the phased sequence, drive adjacent pixel groups of the premod display according to an OR-function of premod versions of respective portions of each of at least the leading bitplane and the following bitplane.