Embodiments of the disclosure relate to an organic light emitting display panel and an organic light emitting display device including the same, and more specifically, to an organic light emitting display panel and an organic light emitting display device which include: an insulation film with at least one concave portion including a flat portion and an inclined portion surrounding the flat portion in at least one subpixel, a first electrode disposed on the concave portion, an organic layer disposed on the first electrode, a second electrode disposed on the organic layer, an encapsulation layer disposed on the second electrode, and at least one structure disposed on the encapsulation layer, overlapping at least one light emitting area, and having at least a side surface where a light reflecting member is disposed, thereby enhancing light extraction efficiency.

A method for charging a pixel and an enlarged pixel of the display device and a display device are provided. The enlarged pixel has a storage capacitance greater than a storage capacitance of the pixel, and the method includes charging the enlarged pixel in a greater amount of time than charging the pixel. Therefore, according to the display device of the disclosure, an image sensing unit may be configured under the enlarged pixel so as to implement an image sense function under a screen.

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. The holding stage includes N stages arranged in sequence, N≥1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2.

A display device includes a substrate including a display area in which a plurality of sub-pixels are disposed, a plurality of anode electrodes respectively connected to the plurality of sub-pixels, and a cathode electrode connected to the plurality of sub-pixels and spaced apart from each of the plurality of anode electrodes. Each of the plurality of anode electrodes is disposed closer to the substrate than the cathode electrode by a height difference compensation part.

Disclosed is an electroluminescent display device using a variable refresh rate (VRR) mode. The purpose of the present disclosure is to reduce the occurrence of a difference in luminance at a time point of a refresh rate change, thereby preventing viewers from perceiving the variation of the refresh rate.

The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.

A capacitor device includes two top capacitor electrodes separated from each other and symmetrical to each other, two intermediate capacitor electrodes symmetrical to each other and respectively overlapping the top capacitor electrodes, a bridge coupling the intermediate capacitor electrodes without overlapping the top capacitor electrodes, and a driving voltage line coupled to the bridge and configured to apply a common voltage to the intermediate capacitor electrodes.

An array substrate is provided, including: a base substrate including a display area; a racetrack hole portion in the display area, including: a long axis; a short axis; a first hole and a second hole; a frame area surrounding the first hole and the second hole; and multiple lines in the frame area. The frame area includes a first wiring area and a second wiring area, the first wiring area includes a first conductive layer, and the multiple lines located in the first wiring area are arranged in the first conductive layer; and the second wiring area includes a second conductive layer and a third conductive layer arranged in different layers, and some of the multiple lines located in the second wiring area are arranged in the second conductive layer, and other lines of the multiple lines located in the second wiring area are arranged in the third conductive layer.

A display panel includes a substrate, a plurality of pixel driving circuits, a plurality of first data lines, a plurality of second data lines and at least one shielding line. A first data line in the plurality of first data lines is electrically connected to pixel driving circuits in even-numbered rows in a same column of pixel driving circuits. A second data line in the plurality of second data lines that is arranged adjacent to the first data line is electrically connected to pixel driving circuits in odd-numbered rows in a same column of pixel driving circuits. The first data line and the second data line have an overlapping area therebetween. The at least one shielding line is configured to transmit a fixed voltage. The at least one shielding line constitutes a first capacitor with the first data line, and/or a second capacitor with the second data line.