A display device includes a display area including a plurality of pixels and a plurality of scan lines connected to the plurality of pixels, and a driving circuit portion that generates a compensation data voltage to compensate for a difference in length between the plurality of scan lines to input the compensation data voltage to a pixel disposed in a first area, based on start scan line information indicating a start of the first area including scan lines of the plurality of scan lines, and end scan line information indicating an end of the first area.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

A display device includes a first switching element including a second electrode and a first gate electrode, a second switching element including a third electrode connected with the first gate electrode, a third switching element including a fifth electrode connected with the second electrode, and sixth electrode, a fourth switching element including a seventh electrode connected with the second electrode, and an eighth electrode, a fifth switching element including a ninth electrode connected with the second electrode, and a tenth electrode, a first light emitting diode connected with the sixth electrode and the eighth electrode, a second light emitting diode connected with the eighth electrode and the sixth electrode, and a switch selectively connecting a common power source line with the sixth electrode or the eighth electrode. The first light emitting diode and the second light emitting diode have different polarities from each other with respect to a same direction.

An electronic device includes a first source group and a second source group, each of which includes a plurality of source channels, and a gamma block that receives first to 2i-th initial voltages (i being an integer of 1 or more), outputs first to 2i-th intermediate voltages by amplifying the first to i-th initial voltages, and outputs first to i-th gamma voltages to the first source group by buffering the first to 2i-th intermediate voltages, and a first buffer block that receives the first to 2i-th intermediate voltages from the gamma block and buffers the first to 2i-th intermediate voltages so as to be output to the second source group, and the gamma block may include a first resistor string including a plurality of resistors connected between nodes from which the first to i-th gamma voltages are output.

Methods and apparatuses relating to controlling an emission of a display panel. In one embodiment, a display driver hardware circuit includes row selection logic to select a number of rows in an emission group of a display panel, wherein the number of rows is adjustable from a single row to a full panel of the display panel, column selection logic to select a number of columns in the emission group of the display panel, wherein the number of columns is adjustable from a single column to the full panel of the display panel, and emission logic to select a number of pulses per data frame to be displayed, wherein the number of pulses per data frame is adjustable from one to a plurality and a pulse length is adjustable from a continuous duty cycle to a non-continuous duty cycle.

A display apparatus includes a display panel displaying an image based on an input image data, a data driver outputting a data voltage to a data line, and a driving controller determining a driving frequency of the display panel based on the input image data. The driving controller includes a flicker value storage configured to store flicker values for grayscale values corresponding to the input image data, a voltage drop determiner configured to adjust a flicker value of the flicker values based on a voltage drop of the display panel, a still image determiner configured to determine whether the input image data is a still image or a video image, and a driving frequency determiner configured to determine the driving frequency of the display panel using the flicker value based on the input image data being the still image.

The present disclosure relates to a drive circuit, including: a first module, generating display data based on image information; a second module, generating a display signal based on the display data and a plurality of clock signals; a third module, outputting a constant current based on the display signal; and a fourth module, configured to provide a reference current to the third module, wherein the fourth module includes: a reference voltage generation module, a bias module, a current generation module, and a pre-charging module. Any two adjacent clock signals of the plurality of clock signals differ by M complete clock cycles, where 0≤M<1. This circuit can realize relatively high image display accuracy with relatively low system power consumption and chip cost, and meanwhile realize effective low grayscale compensation for image.

A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

Provided are a driving method for a display panel, display driving device and electronic apparatus. The display panel includes a shift register. A drive signal of the shift register includes a trigger signal and a clock signal. The driving method includes: a current FPS in a current display mode is acquired; a current trigger signal and a current clock signal of the shift register is determined according to the current FPS; the shift register is provided with the current trigger signal and the current clock signal. A refresh frequency of the current trigger signal is the same as the current FPS. The current clock signal is the same as a reference clock signal in a reference display mode at least within an effective action duration of the current trigger signal. The current FPS is less than or equal to the reference FPS in the reference display mode.