A pixel of a display device includes a light-emitting diode and a pixel circuit that provides a current corresponding to a data signal to the light-emitting diode in response to a plurality of scan signals and a light emission control signal. The light emission control signal includes a first section and a second section, the second section includes a light-emission-on section and a light-emission-off section, the light emission control signal has an active level in the light-emission-on section and has an inactive level in each of the first section and the light-emission-off section, and the light-emission-on section and the light-emission-off section of the light emission control signal may vary depending on a light emission ratio of a dimming mode.

A driving method of a display panel is provided. The driving method of the display panel includes: within one frame, in a charging period of sub-pixels electrically connected to an i.sup.th scan line, each multiplexing circuit charging N data lines electrically connected to the multiplexing circuit in a charging sequence of a first preset sequence; in a charging period of sub-pixels electrically connected to a j.sup.th scan line, each multiplexing circuit charging the N data lines electrically connected to the multiplexing circuit in a charging sequence of a second preset sequence; the second preset sequence is different from the first preset sequence, and charging rankings of each data line electrically connected to each multiplexing circuit in at least two charging sequences are different, where N is an integer and N≥2, and i and j are positive integers and j≠i.

A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

Embodiments of the present disclosure provide a gamma voltage correction method and device, and a display device, wherein a candidate refresh rate last determined in a current frame period of a display panel is used as a target refresh rate, and a gamma voltage corresponding to the target refresh rate is used as a gamma voltage at a display phase in a next frame period of the display panel to perform brightness correction, so that flashing of the display panel during refresh rate switching is prevented, and storage resources are saved.

The present application discloses a display panel driving circuit and a display panel. The display panel driving circuit includes a driving circuit and a light-emitting diode. The driving circuit is connected to the light-emitting diode. The driving circuit includes a plurality of superimposed driving modules, and a corresponding number of driving modules are selectively conducted according to a preset grayscale. Each driving module includes a scan control transistor, a switch transistor and a drive transistor, in each driving module the scan control transistor is connected to the drive transistor via the switch transistor, in each driving module a first end of the scan control transistor is connected to a scan signal terminal, and the light-emitting diode and the drive transistors of the driving modules are sequentially connected. The present application can better increase the number of grayscales, thereby improving image quality.

A display device includes a display panel, a display driver integrated circuit and a driving control circuit. The display panel includes a plurality of pixels connected to a plurality of driving lines and a plurality of source lines. The display driver integrated circuit includes a driving control signal generator. The driving control signal generator generates a driving control signal based on display device information and pixel values corresponding to at least a portion of the plurality of rows among a plurality of previous pixel values of a previous frame and a plurality of present pixel values of a present frame. The driving control circuit selectively connects the display driver integrated circuit with each of the plurality of driving lines based on the driving control signal such that first driving signals provided to first driving lines among the plurality of driving lines are blocked.

The application provides a display panel and a driving method thereof. The display panel comprises a plurality of sub-pixels arranged in a matrix, and the sub-pixels are grouped into a plurality of cell areas arranged repeatedly along the row direction and the column direction. Each cell area comprises at least two sub-pixels, with polarities of adjacent sub-pixels opposite to each other. For at least two consecutive frames during a display cycle, the gray-levels of sub-pixels in the cell area maintain unchanged while polarities of the sub-pixels are reversed.

The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

A display device that includes pixel circuits, in each of which a plurality of types of transistors coexist, and that operates normally is implemented while suppressing an increase in processing cost.

Each unit circuit includes a first control circuit (311), a first output circuit (321), and a second output circuit (322). The first output circuit (321) includes a first output terminal (38) connected to a first scanning signal line; a P-type transistor (M4) having a control terminal connected to a first internal node (N1), a first conductive terminal to which a gate high potential (VGH) is provided, and a second conductive terminal connected to the first output terminal (38); and a N-type transistor (M5) having a control terminal connected to the first internal node (N1), a first conductive terminal connected to the first output terminal (38), and a second conductive terminal to which a gate low potential (VGL) is provided.

A driving device of a display panel and a display device are provided. A source driver expands display data of a low-resolution image to be displayed in a first working mode, and cooperates with the source driver to receive and processes display data of a high-resolution display image in a second working mode, which makes the driving device of the display panel has good compatibility.