A display apparatus includes a substrate including a trench portion, a display area, and a non-display area. The non-display area includes a first non-display area. The display area includes a main area and first and second display areas protruding from the main area. The first non-display area and the trench portion are between the first and second display areas. The display apparatus further includes: first scan lines transmitting scan signals to pixels in the first display area; second scan lines transmitting scan signals to pixels in the second display area; connection scan lines in the first non-display area and connecting the first scan lines and the second scan lines; and driving voltage lines transmitting driving voltages to pixels in the main area. A plurality of first driving voltage lines among the driving voltage lines extend to the first non-display area, and overlap the plurality of connection scan lines.

A display panel. The display panel includes a base substrate, drive circuits, pixel circuits, and signal line groups. The drive circuits and the pixel circuits are arranged on the base substrate. The drive circuits provide control signals for the pixel circuits. The pixel circuits provide drive currents for light-emitting elements of the display panel. The drive circuits include a first drive circuit and a second drive circuit. The signal line groups include a first signal line group and a second signal line group. The first signal line group includes M signal lines that provide signals for the first drive circuit. The second signal line group includes N signal lines that provide signals for the second drive circuit, M≥1, and N≥1. The first drive circuit provides a light-emitting control signal for a light-emitting control transistor of the pixel circuit.

To provide a highly browsable data processing device, provide a highly portable data processing device, provide a data processing device which consumes low power, or provide a data processing device having high display quality, the data processing device includes a display portion having flexibility, a plurality of driver circuit portions arranged in the periphery of the display portion, a sensor portion discerning an external state of the display portion, an arithmetic portion supplying image data to the driver circuit portions, and a memory portion storing a program executed by the arithmetic portion. A first mode in which the display portion is unfolded or a second mode in which the display portion is folded is sensed by the sensor. Low power consumption processing and degradation correction processing are carried out by the program in accordance with the first mode or the second mode.

A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

A display device includes a substrate, first pixels, second pixels, and third pixels. The substrate has a first pixel area, a second pixel area, and a third pixel area. The first pixels are in the first pixel area and are connected to first scan lines and first emission control lines. The second pixels are in the second pixel area and are connected to second scan lines and second emission control lines. The third pixels are in the third pixel area and are connected to third scan lines and third emission control lines. The second scan lines are spaced apart from the third scan lines, and the second emission control lines are spaced apart from the third emission control lines.

Embodiments of the disclosure provide a display substrate and a driving method thereof, as well as a display device. The display substrate comprises a plurality of select switch arrays and a plurality of selecting control circuits formed on the base substrate. Each select switch array comprises a plurality of select switches, a first terminal of each select switch being connected to a corresponding data line, a second end of each select switch being connected to a same data voltage input terminal, a control terminal of each select switch being connected to a same selecting control circuit. Each data line is connected with two columns of pixels, and the gate lines connected with the two columns of pixels are different. Each selecting control circuit is connected to a plurality of selecting control signal input terminals and a corresponding select switch array.

A display device includes a substrate including a first pixel area, a second pixel area, and a third pixel area, each of the second and third pixel areas having a smaller surface area than the first pixel area and being connected to the first pixel area, first to third pixels provided in the first to third pixel areas, respectively, first to third lines connected to the first to third pixels, respectively, a line connecting part connecting the second and third lines, and a dummy unit overlapping the line connecting part to compensate for a difference of a load value of the first line and a load value of the second line.

A display device is disclosed, and the display device includes a substrate including first to third display regions, the second and the third display regions being spaced from each other, each of the second and third display regions having an area smaller than that of the first display region and being continuous to the first display region, first to third pixels in the first to third display regions, first to third lines connected to the first to third pixels, and a dummy part configured to compensate for a difference between a load value of the first lines and load values of the second and third lines, wherein the second display region includes a first sub-region adjacent to the first display region and a second sub-region spaced from the first display region, and the third display region includes a third sub-region adjacent to the first display region and a fourth sub-region spaced from the first display region.

According to one embodiment, a display device includes substrates with pixels, a pixel electrode in each of the pixels, a display select circuit connected to the electrode, which supplies display and non-display voltages, a power line to which first and second voltages are supplied, a memory device connected to the power line and the display select circuit, a voltage select circuit which selects a voltage to be supplied to the power line from the first and second voltages, and a clock circuit which generates a clock signal. The memory device controls the display select circuit using the first and second voltages, and the first voltage select circuit selects the first or second voltages in synchronism with the clock signal.

A display panel includes a plurality of pixels including at least four even-numbered subpixels. The at least four even-numbered subpixels includes: a first red subpixel including a pixel electrode electrically connected to a switching element which is connected to a first data line and a first gate line; a first green subpixel including a pixel electrode electrically connected to a switching element which is connected to a second data line and a second gate line, where the second data line is disposed adjacent to the first data line; a first blue subpixel including a pixel electrode electrically connected to a switching element which is connected to the first data line and the second gate line; and a first multi-primary subpixel including a pixel electrode electrically connected to a switching element which is connected to the second data line and the first gate line.