A driving circuit and a display panel are disclosed. The driving circuit includes a plurality of cascaded driving units. The driving unit includes a forward/backward scan control module, a first control node controlling module, a second control node controlling module, a global control module, a regulating module, a first output module configured to output a stage signal, and a second output module configured to output a gate driving signal. A voltage level of the gate driving signal is higher than a voltage level of the stage signal.

A display panel, a driving method and a display device are disclosed. The display panel is divided into a first area and a second area arranged along a data line direction. Multiple sub-pixels corresponding to a same row of scan line are connected to data lines in one-to-one correspondence. In the first area and second area, each column of sub-pixels is arranged between two adjacent data lines, where the same column of sub-pixels includes multiple sub-pixel groups, each of which includes at least one sub-pixel. Among two adjacent data lines, one data line is connected with the sub-pixels in the odd groups, and the other is connected with the sub-pixels in the even groups. The sub-pixel groups in the first area and the corresponding sub-pixel groups in the second area are axially symmetrical with respect to a boundary line between the first area and the second area.

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

A display device of the present invention includes a pixel unit including a plurality of pixels connected to data lines and scan lines; a data driver disposed on one side of the pixel unit to drive the data lines; a scan driver disposed on the one side of the pixel unit together with the data driver to drive the scan lines; and a controller which controls an output timing of a data signal in units of pixel columns and units of pixel rows based on a load of a scan signal supplied to the scan lines and a load of the data signal supplied to the data lines.

The present disclosure provides a driving method of a gate driving circuit. The driving method includes: outputting, by a plurality of shift register units of a shift register, signals sequentially, the plurality of shift register units being cascaded; determining, by a detection module, whether the plurality of shift register units has an abnormality according to one or more signals outputted from at least a part of the plurality of shift register units, and issuing a scan control command when it is determined that the plurality of shift register units has the abnormality; and controlling, by a scan control module, the shift register to perform forward scanning and reverse scanning under the scan control command.

A display panel includes a source driving circuit, a multiplexer circuit, and multiple sub-pixels arranged in an array. The multiplexer circuit is configured to, under the control of a first multiplexing signal to an Nth multiplexing signal, control the source driving circuit to be connected with sub-pixels of one or more columns; and in a jth frame, a multiplexing signal turn-on sequence for sub-pixels of an odd row is from a Jth multiplexing signal to sequentially increasing to the Nth multiplexing signal and from the first multiplexing signal to sequentially increasing to a (J−1)th multiplexing signal, and a multiplexing signal turn-on sequence for sub-pixels of an even row is completely opposite to the multiplexing signal turn-on sequence for the sub-pixels of the odd row.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

The present disclosure provides a gate driver on array (GOA) circuit and a display panel. The GOA circuit includes multi-level cascaded GOA units. Each of the GOA units includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module and a bootstrap capacitor. By sharing part of the circuit, each of the GOA units can realize multi-level scanning signal outputting, which simplifies the structure of the GOA circuit and further realizes a narrow frame design of display panels.

A display device and a driving method of the same are proposed, the display device including first and second display panels displaying one image in a division manner; first and second data drivers supplying data voltages to the first and second display panels, respectively; first and second scan drivers supplying scan signals to the first and second display panels, respectively; and first and second timing controllers controlling the first and second data drivers and the first and second scan drivers, respectively, wherein the first data driver latches a first data signal output from the first timing controller in a first direction and converts the first data signal to a first data voltage to be outputted, and the second data driver latches a second data signal output from the second timing controller in a second direction and converts the second data signal to a second data voltage to be outputted.

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.