The present disclosure provides a gate driver on array (GOA) circuit and a display panel. The GOA circuit includes multi-level cascaded GOA units. Each of the GOA units includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module and a bootstrap capacitor. By sharing part of the circuit, each of the GOA units can realize multi-level scanning signal outputting, which simplifies the structure of the GOA circuit and further realizes a narrow frame design of display panels.

There are disclosed a gate driving circuit and a display device, which include: M areas, each area includes K sub driving circuit, and the k-th sub driving circuit includes: first and second row driving circuits, both of which include: a gate line grating control module (11) including a row control signal input terminal and an area grating signal input terminal, and an output terminal of the gate line grating control module (11) outputs a gate line grating signal according to received k-th and (k+1)-th row control signals and area grating signal; and a gate driving signal output module (12) including a gate line grating signal input terminal, a first-level driving signal input terminal and a second-level driving signal input terminal, and an output terminal of the gate driving signal output module (12) is connected to the gate line. The gate driving circuit can enhance flexibility of a scanning mode.

A display apparatus includes: a modular display panel including a plurality of display modules; and a timing controller. Each of the plurality of display modules includes: a display panel including a pixel array and subpixel circuits; and a driving unit which drives the subpixel circuits such that inorganic light-emitting elements in the pixel array successively emit light in a first order of multiple row lines or in a second order opposite to the first order. The timing controller provides the driving unit of a first display module with first control signals for causing the inorganic light-emitting elements of the first display module to emit light in the first order, and provides the driving unit of a second display module, which is positioned above or below the first display module, with second control signals for causing the inorganic light-emitting elements of the second display module to emit light in the second order.

A display device and a driving method of the same are proposed, the display device including first and second display panels displaying one image in a division manner; first and second data drivers supplying data voltages to the first and second display panels, respectively; first and second scan drivers supplying scan signals to the first and second display panels, respectively; and first and second timing controllers controlling the first and second data drivers and the first and second scan drivers, respectively, wherein the first data driver latches a first data signal output from the first timing controller in a first direction and converts the first data signal to a first data voltage to be outputted, and the second data driver latches a second data signal output from the second timing controller in a second direction and converts the second data signal to a second data voltage to be outputted.

The present invention provides a scanning driver and an organic light-emitting display using the same. The scanning driver comprises a plurality of cascaded structures receiving signals from a first timing clock line (CK1) and a second timing clock line (CK2) with opposite phases, the cascaded structures successively generating output signals (i.e., scanning signals), wherein each of the cascaded structures comprises: a first transistor, connected to a starting signal line or to a scanning output line of a previous cascaded structure; a second transistor, connected to the second timing clock line and to the scanning output line; a third transistor connected to a high-level power supply VGH; a fourth transistor, connected to a low-level power supply VGL and to an output terminal of the third transistor; a fifth transistor, connected to a high-level power supply VGH and to a scanning output line; and a first capacitor, connected between an output terminal of the first transistor and the scanning output line. Arranging a first capacitor C1 between the output terminal of M1 and the scanning output line prevents slight-ON of M2, thus reducing the reverse current at the scanning driver and reducing the power consumption.

Provided is a display device and the like, in which power consumption is reduced in consideration of increased definition of a display image or an increased size of a display panel. In a liquid crystal display device having a power-saving mode in addition to a normal mode, buffers for outputting data signals from a source driver (300) to source lines are made up of positive-polarity buffers (333p) and negative-polarity buffers (333n), and a connection switching circuit 334 is provided between output ends of these buffers and the source driver (300). In the power-saving mode, the buffers (333p, 333n) are connected to source lines by the connection switching circuit (334), while the polarities of the buffers are taken into account, such that the same data signals are applied to two mutually adjacent source lines. Accordingly, although horizontal resolution is halved, half of the buffers in the source driver (300) are halted, thereby enabling great reduction in power consumption.

The display device includes: a scan line driving circuit selecting a potential supplied to a scan line; a driver chip; a plurality of source wires connected to a detection circuit; a terminal connected to an inspection wire controlling the scan line driving circuit; and a protection circuit arranged between the inspection wire and the terminal When it is assumed that an extending direction of a switch circuit connected with the plurality of source wires is an X axis direction, that one side of the X axis direction is an X1 side, and that the other side therein is an X2 side, the plurality of source wires are arranged closer to the X1 side than a center of the region in the X axis direction, and the terminal and the protection circuit are arranged closer to the X2 side than the center of the region in the X axis direction.

Discussed is a shift register capable of reducing a circuit area through simplification of a logic circuit configuration. The shift register according to an embodiment includes stages each selectively executing a forward scan and a backward scan. Each stage includes a pull-up transistor for generating a first clock under control of a control node, as an output thereof, a pull-down transistor for generating a gate-off voltage under control of a third clock, as an output thereof, a first transistor for setting and resetting the control node during the forward scan while resetting the control node during the backward scan, under control of a fourth clock, using output signals from a previous stage, and a second transistor for setting and resetting the control node during the backward scan while resetting the control node during the forward scan, under control of a second clock, using output signals from a next stage.

The invention discloses a gate driving circuit and a display device. The gate driving circuit includes first to eighth dock signal lines and first to N.sup.th stage first shift registers, where N is an integer greater than or equal to 9. The first to eighth clock signal lines are configured to provide first to eighth clock signals, respectively. The i.sup.th stage first shift register is coupled to one of the first to eighth clock signal lines and receives one of the first to eighth clock signals, a first input signal and a second input signal and outputs an i.sup.th stage first output signal, where i is any integer from 1 to N.

A display device includes a plurality of pixel circuits and a gate driver including a plurality of stages configured to output a gate signal to a plurality of gate lines, respectively, to provide the gate signal to the pixel circuits. Each of the stages is divided into a plurality of sub-blocks. At least one of the pixel circuits is located between two adjacent sub-blocks of the sub-blocks.