A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

The present embodiments disclose a pixel driving circuit. A pixel driving circuit according to an embodiment of the present disclosure is electrically connected to a luminous element and comprises a first circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes included in a frame, a second circuit configured to store bit values of multi-bit data in the frame and generate the control signal based on the stored bit values, and a clock signal such that each subframe included in the frame is controlled according to each bit value, and wherein each of the plurality of subframes includes a data-writing period and a light-emitting period, during the data-writing period of each subframe, the second circuit receives and stores a corresponding bit string from among a plurality of bit strings of n-bit data, wherein the plurality of bit strings are generated by a combination of bits in the number of n, which is smaller than m, from among m bits constituting a bit string of the multi-bit data, and the n-bit data is a bit string in which n bits from among the m bits are combined such that a difference in light-emitting periods of the plurality of subframes is minimized.

Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

The present embodiments may provide a touch display device including: a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of touch electrodes are disposed; a gate-driving circuit configured to drive the plurality of gate lines; a data-driving circuit configured to drive the plurality of data lines; and a touch-driving circuit configured to drive the plurality of touch electrodes while the plurality of data lines and the plurality of gate lines are driven. In this touch display device, while a touch-driving signal swings with a predetermined amplitude, a data signal and a gate signal may also swing with the predetermined amplitude. According to the present embodiments, it is possible to enable high-speed image display and high-speed touch sensing, to perform a display operation and a touch operation simultaneously, and to display an image normally without any image change.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

The invention relates to a source driver and a composite level shifter. The source driver comprises a data buffer circuit, a plurality of level shifters and a plurality of driving circuits. The data buffer circuit receives and registers a plurality of pixel data during a driving period. The level shifters convert the voltage levels of the pixel data registered in the data buffer circuit during the driving period. The driving circuits generate a plurality of source signals according to the converted pixel data during driving period. The data buffer circuit may comprise a plurality of composite level shifters for converting the voltage levels of the pixel data, and latching the converted pixel data.

An organic light emitting diode (OLED) display device includes a first power supply circuit configured to generate a pixel driving voltage, a display panel configured to receive the pixel driving voltage from the first power supply circuit, and including a plurality of pixels each configured to emit light based thereon, and a scan driver configured to receive the pixel driving voltage from the display panel, and to provide scan signals based on the pixel driving voltage to the plurality of pixels.

A display device includes: a pixel part to display an image and including pixels receiving a reference voltage; a controller to determine a value of the reference voltage based on a load of the entire pixel part, and to control a grayscale range of image data according to a location in the pixel part based on the reference voltage; a data driver to supply data voltages to the pixel part through data lines based on grayscale ranges adjusted for each location in the pixel part; and a scan driver to supply a scan signal to the pixels through scan lines.

A system for generating a voltage at a pixel array includes a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel. The system further comprises a row formatter configured to store a plurality of bits representing image data for a row of display pixels of the LCOS array; a row controller configured to write a subset of the plurality of bits representing image data for a pixel of the row into a plurality of data latches of said pixel circuit; and a waveform generator for generating reference pulses represented by a set of reference bits. The pixel circuit is configured to compare each reference bit to corresponding bits stored in the latches of each pixel circuit, and generate voltage at an electrode of each pixel based on this comparison.

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.