The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.

In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A display device can include a timing controller; a level shifter including a signal input circuit to receive a first clock signal and a second clock signal, a driving mode conversion circuit to self-generate one or more mode signals based on the first and second clock signals for adjusting a driving mode, and a signal output circuit to generate a plurality of scan clock signals based on the one or more mode signals, the first and second clock signals; a shift register configured to generate a scan signal based on the plurality of scan clock signals; and a display panel configured to display an image based on the scan signal. Also, the level shifter is configured to in response to a width of a pulse of the first clock signal being greater than a threshold value, sequentially output a pulse for each of the plurality of scan clock signals.

Disclosed is a display apparatus which may prevent a settling time from being changed when image data input to a source drive integrated circuit (IC) is changed, for voltage interpolation. The display apparatus includes a source drive integrated circuit (IC) configured to sequentially perform a first voltage interpolation and a second voltage interpolation at every horizontal period so as to drive a data line by using N bit image data including an M bit interpolation code and an N-M bit image code.

The present disclosure relates to a power management circuit including a multiplexer and a power converter, and can provide technology that implements a multiplexer selecting and outputting input power to the power management circuit and a power converter controlling input voltage of a timing controller as one integrated circuit.

The present disclosure relates to an electroluminescent display device and a method for sensing electrical characteristics thereof, and the electroluminescent display device includes a display panel including a plurality of pixels including a sensing pixel and a non-sensing pixel connected to each data line, the plurality of pixels sharing one sensing line, a sensing circuit configured to sense an electrical characteristic value of the sensing pixel based on a sensing voltage applied to the shared sensing line, and a feedback unit configured to apply a feedback voltage according to the sensing voltage applied to the shared sensing line to the data line of the non-sensing pixel.

The present disclosure provides a display panel and a display device. The display panel includes source driver chips. The source driver chips include charging compensation modules, and each of the charging compensation modules includes: a plurality of shift registers cascadely connected and configured to time-divisionally output a plurality of pulse signals, and a plurality of level shift circuits time-divisionally conducted in response to the plurality of the pulse signals to prevent the plurality of the level shift circuits in the source driver chips from outputting and generating a plurality electron currents at a same time, which would result in a superposition of current peaks and cause electromagnetic interference problems.

A gate driving circuit and a display device including the same are disclosed. The gate driving circuit includes a plurality of signal transmitters which are cascade-connected via a carry line to which a carry signal is applied from a previous signal transmitter, and a repair line connected to the plurality of signal transmitters, wherein a signal transmitter includes a circuit part to receive the carry signal from the previous signal transmitter, and charge or discharge a first control node and a second control node, an output part to output a gate signal and a carry signal based on potentials of the first control node and the second control node, and a repair block connected to the repair line and to output a repair gate signal replacing the gate signal and a repair carry signal replacing the carry signal when a logic signal is applied from the repair line.