The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A driving circuit that includes a timing controller, a selecting module connected to the timing controller, and a level shifter connected to the selecting module, wherein the timing controller includes N pins, each of the pins provides a clock signal, and N is a positive integer; the selecting module includes N selecting units, an input terminal of each of the selecting units is connected to a corresponding pin of the timing controller, output terminals of each of the selecting units are connected to M input pins of the level shifter, and M is greater than or equal to 2. The driving circuit according to the present invention individually passes clock signals of a timing controller through selecting units and outputs to a level shifter, and pins of the timing controller can be substantially saved.

There is provided a voltage supply circuit, in which a signal output end of a power management integrated circuit, a signal input end of a transmission branch, and a signal input end of a voltage reduction branch are coupled to a first node; a signal output end of transmission branch and a signal output end of the voltage reduction branch are coupled to a second node; the power management integrated circuit supplies an initial voltage to the first node; the transmission branch is coupled to a control signal terminal, and switch between a conducting state and a cutoff state in response to control of a control signal, and write the initial voltage into the second node in the conducting state; and the voltage reduction branch performs voltage reduction on the initial voltage at the first node to obtain a reduced voltage to be written into the second node.

A power circuit according to the present disclosure may include a multiplexer connected to a first power line and a second power line and selecting and outputting one of a first voltage supplied through the first power line and a second voltage supplied through the second power line. Further, the power circuit may include a first power circuit which generates a first driving voltage and a second driving voltage by using a voltage supplied from the multiplexer, recognizes whether there is the first voltage supplied through the first power line, and does not output the first driving voltage when the first voltage is not recognized.

According to one embodiment, a display panel includes scanning lines, signal lines, a pixel switching element, a pixel electrode, and a first control switch including first control switching elements. Each of the first control switching elements is composed of a transistor and includes a gate electrode, a source electrode, and a drain electrode. The scanning lines electrically connected to the gate electrodes of the first control switching elements are different from each other. The drain electrodes of the first control switching elements are electrically bundled and are connected to power source voltage output terminal of the first control switch.

A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

A clock and voltage generation circuit includes a voltage generator which generates a first gate high voltage, a first gate low voltage, a second gate high voltage, and a second gate low voltage, a first level shifter which generates a first gate clock signal which swings between the first gate high voltage and the first gate low voltage in synchronization with a gate pulse signal, and a second level shifter which generates a second gate clock signal which swings between the second gate high voltage and the second gate low voltage in synchronization with the gate pulse signal. The voltage generator lowers the second gate high voltage to a voltage level of a kickback reference voltage in response to a kickback signal, and the first gate low voltage and the second gate high voltage are gate-on voltages, and the first gate high voltage and the second gate low voltage are gate-off voltages.

A display device includes: a cell matrix including a first cell line and a second cell line, wherein the first cell line includes first cells sharing first row lines, and the second cell line includes second cells sharing second row lines; a redundancy integrated circuit including a redundancy cell line including redundancy cells, wherein the redundancy cells share a third row line and are connected to the first and second cells through a plurality of column lines and a plurality of connection lines; and a display driver integrated circuit (DDI) configured to replace the first cell line or the second cell line with the redundancy cell line through the first row lines, the second row lines, and the third row line based on whether the first and second cell lines include a bad cell.

A display driver includes first and second level shifters, respectively receiving a digital signal's most significant bit (MSB) and the digital signal's non-MSB. The first level shifter includes a first input terminal, a first output terminal via which a signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a signal input to the second input terminal is output. The second level shifter includes a third input terminal, a third output terminal via which a signal input to the third input terminal is output, a fourth input terminal, and a fourth output terminal via which a signal input to the fourth input terminal is output. The first input terminal receives an inverted MSB, the second input terminal receives the MSB, the third input terminal receives the non-MSB, and the fourth input terminal receives the inverted non-MSB.

A display panel including a first current source and a first pixel unit is provided. The first pixel unit includes a first switch and a first light-emitting diode. The first switch is coupled to the first current source and receives a first scan signal. When the first scan signal is enabled, the first switch is turned on and receives a first current provided by the first current source. The first light-emitting diode is coupled to the first switch. When the first switch is turned on, the first current passes through the first light-emitting diode to turn on the first light-emitting diode.