A display device includes a display panel, a display driver integrated circuit and a driving control circuit. The display panel includes a plurality of pixels connected to a plurality of driving lines and a plurality of source lines. The display driver integrated circuit includes a driving control signal generator. The driving control signal generator generates a driving control signal based on display device information and pixel values corresponding to at least a portion of the plurality of rows among a plurality of previous pixel values of a previous frame and a plurality of present pixel values of a present frame. The driving control circuit selectively connects the display driver integrated circuit with each of the plurality of driving lines based on the driving control signal such that first driving signals provided to first driving lines among the plurality of driving lines are blocked.

A display device that includes a plurality of scanning lines, a plurality of data lines, and a pixel unit in which a pixel is specified by the scanning line and the data line, in which image data of one line is simultaneously displayed for a plurality of adjacent scanning lines, image data to be simultaneously displayed is made different between an N frame and an (N+1) frame that are temporally consecutive, and the image data is shifted by one line, and the image data of a last scanning line of at least one of the N frame or the (N+1) frame is hidden.

An electronic device that quickly updates a screen when receiving an input from a peripheral device is provided. The electronic device includes a display driver integrated circuit (DDIC) configured to output a tearing effect (TE) signal having a designated frequency, and a processor configured to control the peripheral device, a display, and the DDIC and to transmit image data to the DDIC in response to the TE signal, wherein the DDIC is configured to output the TE signal at a first frequency, receive an interrupt signal from the peripheral device while the TE signal is output at the first frequency, output the TE signal at a second frequency in response to the interrupt signal, the second frequency being greater than the first frequency, receive image data updated by the processor based on the TE signal output at the second frequency, and drive the display to display the received image data.

The present application relates to a sub-pixel rendering method for a display panel, which determines sampling locations according to arrangement locations of the sub-pixels, converts an input image according to a human vision model for correspondingly generating an adjustment luminance data, and samples a plurality of adjustment luminance value of the adjustment luminance data according to the sampling locations. Thereby, corresponded target grayscale data is generated. Thus, the input image is prevented from distortion.

A pixel of display device includes a light emitting element, a first transistor coupled between first power source and a second node and having a gate electrode connected to a first node N1, and the first transistor being configured to control a driving current supplied to the light emitting element in response to a voltage of the first node, a first capacitor including one electrode connected to the first node and another electrode connected to a third node, a second transistor coupled between the third node and a data line, a third transistor coupled between the first node and the second node, a fourth transistor coupled between the first node and an initialization power source, a fifth transistor coupled between a reference power source and the third node, and an eighth transistor coupled between a fourth node and an anode initialization power source.

Systems, methods, and non-transitory media are provided for dynamically switching frame rates without changing a display refresh rate. An example method can include receiving, from a display device associated with a computing device, a set of control signals indicating a display refresh rate implemented by the display device; adjusting a frame rate associated with application data from one or more applications executed on the computing device; synchronizing, based on the set of control signals, the adjusted frame rate with two or more display refresh cycles, each display refresh cycle being based on the display refresh rate; providing, to the display device, a first frame at the adjusted frame rate, the first frame being generated based on the application data; and displaying the first frame at the display device implementing the display refresh rate.

A display device comprising: a display panel to display a frame having a resolution up to a first frame rate; a plurality of image processing units; and a processor. The processor configured to, based on change from a first mode of displaying a content, among a plurality of modes of the display device, to a second mode of displaying plural contents, change frame rates of a plurality of contents output from the plurality of image processing units to a same frame rate, mix the plurality of contents with the frame rates changed to the same frame rate, and change a vertical resolution of the mixed content. The display panel is enabled to output the mixed content, at a second frame rate greater than the first frame rate.

A display device including: pixels coupled to first scan lines, second scan lines, emission control lines, and data lines; a first scan driver configured to supply a first scan signal to each of the first scan lines at a first frequency; a second scan driver configured to supply a second scan signal to each of the second scan lines at a second frequency corresponding to a driving frequency of the pixels; an emission driver configured to supply an emission control signal to each of the emission control lines at the first frequency; a data driver configured to supply a data signal to each of the data lines at the second frequency; and a timing controller configured to control the first scan driver, the second scan driver, the emission driver, and the data driver.

Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically. In accordance with another embodiment, video or graphics may be segmented by a render engine into regions of interest or objects of interest and objects not of interest and again each of the separate regions or objects may be transferred to the display engine as a separate surface. Then the display engine may transfer the separate surfaces to a display controller of a display panel over a display link. At the display panel, a separate frame buffer may be used for each of the separate surfaces.

A pixel includes: a light emitting diode; a first transistor; a first capacitor connected between a first node and a gate electrode of the first transistor; a second transistor including a first electrode electrically connected to the gate electrode of the first transistor, a second electrode and a gate electrode which receives a first scan signal; and a third transistor including a first electrode electrically connected to the second electrode of the second transistor, a second electrode electrically connected to a third voltage line, and a gate electrode which receives a second scan signal. During an initialization period, an initialization voltage provided from the third voltage line is provided to the gate electrode of the first transistor through the third and second transistors, and, when the initialization period is terminated, at least one of the second transistor and the third transistor is turned off.