A data storage device includes a nonvolatile memory device; a control unit configured to generate a descriptor in which works for controlling the nonvolatile memory device are written; a memory control unit configured to provide control signals and write data to the nonvolatile memory device based on the descriptor; and a voltage detector configured to provide a voltage drop signal to the memory control unit in the case where a first operating voltage provided to the memory control unit or a second operating voltage provided to the nonvolatile memory device drops.

A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

According to one embodiment, a first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal. high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories.

Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power source associated with a second voltage higher than the first voltage is available. The memory device may activate a functionality to use the second power source for the access operations if the second power source is available, and the memory device may then perform one or more access operations using the second voltage from the second power source based on the activated functionality.

Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.

The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

An operating method of a memory controller, configured to control a non-volatile memory device that performs a refresh read operation, detects a power on state or power off state of the non-volatile memory device and issues a refresh read command. The non-volatile memory device that receives the refresh read command is controlled to perform, one time, the refresh read operation including a read operation on one of a plurality of word lines with respect to each of the plurality of memory blocks.