Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.

Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

Provided are a power failure protection method and solid state drive (SSD) The SSD comprises: a power-failure detection device, for monitoring in real time whether the power supply is abnormal; a power-failure protection device performs a power-failure protection operation when the power supply is monitored to be abnormal: breaking a connection with a host system bus, an SSD internal clock breaking from a system bus clock and writing data in the SSD cache into a storage unit of the SSD by using the SSD internal clock. The technical solution ensures completion of the data protection operations by utilizing a remaining capacity, thus ensuring data integrity.

A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC1) indicating a number of memory cells turned ON by a first read voltage and a second ON cell count (OCC2) indicating a number of memory cells turned ON by a second read voltage among the memory cells connected to a reference word line. The controller stores the OCC1 for each of the memory blocks in the PLP area when a sudden power off occurs in the storage device.

A memory system and method for fast firmware download are provided. In one embodiment, a memory system is presented comprising non-volatile memory, volatile memory, and a controller. The controller is configured to receive a boot loader and firmware; store the boot loader and firmware in the volatile memory; execute the boot loader, wherein executing the boot loader causes the controller to read the firmware from the volatile memory, decompress the firmware, and store the decompressed firmware in the volatile memory; and copy the compressed firmware from the volatile memory to the non-volatile memory. Other embodiments are provided.

A power device includes a lithium ion capacitor and a regenerative LIC whose capacity is lower than that of the lithium ion capacitor. The power device further includes a diagnosis circuit and a charge circuit. The diagnosis circuit performs a life diagnosis on the lithium ion capacitor by using electricity that is discharged from the lithium ion capacitor and charges the regenerative LIC with the electricity used for the life diagnosis. The charge circuit charges the lithium ion capacitor with the electricity that is output from the regenerative LIC.

Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.