A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.

According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.

The system contains at least one basic block formed by a first multiplexer having an output is connected to a flag register memory, implemented as a LUT table. An output of a circuit for write permit to the memory is connected to the input of the write signal to the memory, which is further equipped with the clock signal input and the data input. The data output from the memory of each basic block is connected to a masking block relevant for the given basic block. The outputs of these masking blocks are connected to the inputs of the second multiplexer, while its output is the output of the system of flags. The input of the control signal for writing to the memory of each basic block is connected to the output of the demultiplexer and to the second input of the masking block for the given basic block.

An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.