A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.

A semiconductor device includes a mode control circuit, a write control circuit and an internal data generation circuit. The mode control circuit activates a pattern input mode according to a logic level combination of a chip selection signal, configured to activate a command/address signal to generate an operation set signal from the command/address signal. The mode control circuit generates a mode control signal, which is enabled by the operation set signal, according to a logic level combination of the chip selection signal and the command/address signal, in a write mode after the pattern input mode is activated. The write control circuit generates a write enablement signal, which is enabled according to a logic level of the mode control signal. The internal data generation circuit generates internal data to be stored into a core circuit according to the write enablement signal.

A semiconductor device includes a pre-shift circuit and a shift circuit. The pre-shift circuit shifts an internal write signal by a pre-shift period to generate a pre-write signal. The shift circuit shifts the pre-write signal by a shift period to generate a shift write signal for generating a column selection signal. The column selection signal is activated to select a column path through which data are inputted or outputted. The pre-shift period is set as a period corresponding to a multiple of L times a cycle of a clock signal, wherein L is a natural number which is equal to or greater than two.

Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.

Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

A strobe generation circuit includes: a main hybrid multiplexing circuit outputting a main pull-up signal and a main pull-down signal to first and second nodes, respectively, the main pull-up and pull-down signals being selectively controlled based on first pull-up and pull-down control signals generated by removing an input loading of main data; a sub hybrid multiplexing circuit outputting a sub pull-up signal and a sub pull-down signal to the first and second nodes, respectively, the sub pull-up and pull-down signals being selectively controlled based on second pull-up and pull-down control signals generated by removing an input loading of sub data; a latch circuit latching a signal of the first node and a signal of the second node to output a first latch signal and a second latch signal; and an output driver outputting a strobe signal according to the first and second latch signals.

A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.

A semiconductor device includes a repeater configured to output latch data as aligned data when the operation control signal is disabled and configured to interrupt the input of the latch data when the operation control signal is enabled for performing a data masking operation of internal data. The operation control signal is enabled according to logic levels of the internal data when a flag signal is enabled and a write data control signal is enabled.

A semiconductor device, includes: a data input pin; a data output pin; an internal circuit; a register accessible by the internal circuit; and a transceiver circuit including a transfer buffer and configured to: write data input through the data input pin to the transfer buffer, and output the data through the data output pin; and transfer data stored in the transfer buffer to the register when a transfer command is input through the data input pin.