Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

A First In First Out (FIFO) memory includes storage units. Outputs of the storage units are connected to one node. The storage unit includes storage sub-units, a selector, and a drive. An input of the selector is connected to outputs of the storage sub-units. An input of the drive is connected to an output of the selector. Driven by a first pointer signal, the storage sub-units receive storage data. Driven by a second pointer signal, the drive outputs the storage data.

A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.

A network device includes a linear feedback shift register circuit and a value updating circuit. The linear feedback shift register circuit is configured to perform an auto crossover mechanism according to at least one clock signal and a plurality of first bits, in order to control at least one port of a first interface circuit to connect with a second interface circuit. The value updating circuit is configured to perform at least one of a plurality of operations according to exclusive information. The plurality of operations includes: generating a plurality of initial values, in which the value updating circuit is configured to utilize the plurality of initial values to update at least one partial bits of the plurality of first bits; or setting a period of the at least one clock signal, in which the exclusive information includes operational information or production information of the network device.

Embodiments of the present disclosure disclose a shift register unit, a driving method thereof, and a device. The shift register unit includes an input circuit, a node control circuit, a first control output circuit, a second control output circuit and an output circuit. By providing the first control output circuit and the second control output circuit, the first control output circuit and the second control output circuit may operate alternately, so that the first control output circuit and the second control output circuit may have time for characteristics recovery respectively, thus improving the service life and output stability of the shift register unit.

A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.