Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.

A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2.sup.(N-M) th memory state; when the program verification of the 2.sup.(N-M) th memory state is passed, identifiers corresponding to the 1st to 2.sup.(N-M) th memory states stored by the main latch are made different from those corresponding to the 2.sup.(N-M)+1st to 2.sup.N th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N−2).

A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A memory device and a glitch prevention method thereof are provided. The memory device includes a data strobe signal input circuitry, a transfer signal generating circuitry, a data alignment circuitry, and a blocking circuitry. The data strobe signal input circuitry is configured to input a data strobe signal. The transfer signal generating circuitry is configured to generate a transfer signal with pulses in synchronization with rising edges or falling edges of the data strobe signal in response to a transfer command. The data alignment circuitry is configured to align a data signal to be transferred in response to the generated transfer signal. The blocking circuitry is configured to block an input of the data strobe signal over a postamble timing of the data strobe signal according to a number of bursts counted in each time of data transfer.

A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.