In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.

A pipe latch circuit includes a data latch circuit configured to latch an input data based on an input control signal and output the latched input data as a latch data based on an output control signal, a sense amplification circuit configured to sense and amplify the latch data based on a sum output control signal, and a data driving circuit configured to drive an output data from the latch data based on the sum output control signal.

A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).

In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.

Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator of a memory controller can apply a delay to data signals transmitted to a memory circuit based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller or memory circuit powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator or compensation circuits may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic. When the first data is input, the sorter can allow the first data to pass as-is and output the first data as second output data in the form of a direct current of the first logic. When a first edge that changes from the second logic to the first logic is input, the sorter can delay the first edge by synchronizing the same with a rising edge or falling edge of the control pulse, and output the first edge as the second output data.