An optical synapse comprises a memristive device for non-volatile storage of a synaptic weight dependent on resistance of the device, and an optical modulator for volatile modulation of optical transmission in a waveguide. The memristive device and optical modulator are connected in control circuitry which is operable, in a write mode, to supply a programming signal to the memristive device to program the synaptic weight and, in a read mode, to supply an electrical signal, dependent on the synaptic weight, to the optical modulator whereby the optical transmission is controlled in a volatile manner in dependence on programmed synaptic weight.

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.

A memory system includes: a memory device including a memory cell array and a page buffer circuit, the memory device performing a data program operation or a data erase operation, suspending the data program operation or the data erase operation in response to a suspend command, performing a data read operation of storing read data from the memory cell array in the page buffer circuit in response to a read command, and performing a data output operation of outputting the read data stored in the page buffer circuit; and a memory controller outputting a pre-resume command to the memory device between a first time at which the data read operation is complete and a second time at which the data output operation starts.

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

Implementations described and claimed herein provide a high-capacity, high-bandwidth scalable storage device. The scalable storage device includes a layer stack including at least one memory layer and at least one optical control layer positioned adjacent to the memory layer. The memory layer includes a plurality of memory cells and the optical control layer is adapted to receive optically-encoded read/write signals and to effect read and write operations to the plurality of memory cells through an electrical interface.

A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.