Provided herein may be a page buffer, a memory device having the page buffer, and a method of operating the memory device. The page buffer may include a precharger configured to precharge a bit line to a precharge level, a comparison signal output circuit configured to generate a first output signal by comparing a voltage of the bit line with a reference voltage, a pulse width control circuit configured to generate a second output signal by increasing a pulse width of a pulse of the first output signal by a preset multiple, and a register configured to sense data based on a pulse width of the second output signal and output the sensed data.

A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.

A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

A system including a machine learning processing device and a memory device with microbumps is disclosed. A machine learning processing device is for performing a machine learning operation, where the machine learning processing device includes a first set of microbumps. A memory device is for storing data for the machine learning operation, where the memory device includes a second set of microbumps. The first set of microbumps of the memory device are coupled with the second set of microbumps of the machine learning processing device. The first set of microbumps of the memory device and the second set of microbumps of the machine learning processing device are to transmit the data for the machine learning operation.

Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.

A memory device includes an external information input circuit configured to generate a burst mode signal and a write command pulse for a write operation, by receiving external information for the write operation; and a write operation control circuit configured to generate a write control pulse for storing internal data in a cell array, from the write command pulse when a first burst mode is performed on the basis of the burst mode signal, and to control whether to generate the write control pulse from the write command pulse when a second burst mode is performed on the basis of the burst mode signal.

A mask read only memory device is provided. Single-transistor memory cells are arranged in rows and columns. Each word line is associated with a corresponding row. Each bit line is associated with a corresponding column. Each first reference line selectively provides a first potential in a first phase and a second potential in a second phase. Each second reference line selectively provides the second potential in the first read phase and the first potential in the second phase. Each memory cell has a gate coupled to a word line, a drain coupled to a bit line and a source terminal either floating, grounded or coupled to one among a first reference line and a second reference line. One of first to fourth logic values is read during the memory cell.