A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

A memory circuit includes a pre-charging circuit and a control circuit. The pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal. The control circuit is configured to in response to a memory being in a row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.

A compilation method includes: receiving a signal to be compiled and a working frequency signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the working frequency signal to determine a first compilation value.

System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.

A signal sampling circuit and a semiconductor memory device are provided. The signal sampling circuit includes a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a mode selection circuit, configured to determine a target mode clock signal and a target mode chip select signal according to the mode selection signal; a first clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a first chip select clock signal; a second clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a second chip select clock signal; and a command decoding circuit, configured to determine a target command signal.

A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.