An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N.sub.2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N.sub.2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N.sub.2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N.sub.2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

A magnetic device is equipped with a stacked body including a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer; and an insulator which covers at least a part of side surfaces of the stacked body, in which the insulator has a space outside the side surface of the stacked body.

A magnetic device is equipped with a stacked body including a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer; and an insulator which covers at least a part of side surfaces of the stacked body, in which the insulator has a space outside the side surface of the stacked body.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

An object of the invention is to provide a magnetoresistance effect element which includes a reference layer having three or more magnetic layers and which improves a thermal stability factor Δ by decreasing a write error rate using an element structure that enables a wide margin to be secured between a current at which magnetization of the reference layer is reversed and a writing current Ic of a recording layer and by reducing an effect of a stray magnetic field from the reference layer. The magnetoresistance effect element includes: a first recording layer (A1); a first non-magnetic layer (11); and a first reference layer (B1), wherein the first reference layer (B1) including n-number of a plurality of magnetic layers (21, 22, . . . , 2n) and (n−1)−number of a plurality of non-magnetic insertion layers (31, 32, . . . 3(n−1)) adjacently sandwiched by each of the plurality of magnetic layers, where n≥3.

An object of the invention is to provide a magnetoresistance effect element which includes a reference layer having three or more magnetic layers and which improves a thermal stability factor Δ by decreasing a write error rate using an element structure that enables a wide margin to be secured between a current at which magnetization of the reference layer is reversed and a writing current Ic of a recording layer and by reducing an effect of a stray magnetic field from the reference layer. The magnetoresistance effect element includes: a first recording layer (A1); a first non-magnetic layer (11); and a first reference layer (B1), wherein the first reference layer (B1) including n-number of a plurality of magnetic layers (21, 22, . . . , 2n) and (n−1)−number of a plurality of non-magnetic insertion layers (31, 32, . . . 3(n−1)) adjacently sandwiched by each of the plurality of magnetic layers, where n≥3.