A magnetic memory device may include tunnel junction unit cells, each including a pinned magnetic layer, an insulating layer, and a free magnetic layer which are sequentially stacked, a conductive line structure configured to supply an in-plane current to the unit cells and to include an antiferromagnetic layer, which is provided adjacent to the free magnetic layer, and a ferromagnetic layer, which is provided adjacent to the antiferromagnetic layer and has an in-plane magnetic anisotropy, and a voltage applying unit configured to independently apply a selection voltage to each of the tunnel junction unit cells. Each of the tunnel junction unit cells may have a magnetization direction that is selectively changed by the in-plane current and the selection voltage.

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NH.sub.3 gases. The dry chemical gas removal process utilizing HF and NH.sub.3 gases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

The disclosed technology generally relates to magnetic memory and more particularly to voltage-controlled magnetic memory, and to methods of using same. In one aspect, a magnetic memory comprises a first magnetic stack including a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer. The magnetic memory additionally comprises a second magnetic stack including a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer. The first free ferromagnetic layer and the second free ferromagnetic layer of the magnetic memory are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and the first gate electrode and the second gate electrode are electrically isolated from each other.

The disclosed technology generally relates to magnetic memory and more particularly to voltage-controlled magnetic memory, and to methods of using same. In one aspect, a magnetic memory comprises a first magnetic stack including a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer. The magnetic memory additionally comprises a second magnetic stack including a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer. The first free ferromagnetic layer and the second free ferromagnetic layer of the magnetic memory are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and the first gate electrode and the second gate electrode are electrically isolated from each other.

The present technology relates to a storage device that realizes both a high information retention property and a low power consumption. A storage device includes a fixed layer, a storage layer, an intermediate layer, and a heat generation layer. The fixed layer includes a first ferromagnetic layer that includes a fixed perpendicular magnetization. The storage layer includes a second ferromagnetic layer that includes a perpendicular magnetization invertible by a spin injection. The intermediate layer is formed of an insulator and is arranged between the storage layer and the fixed layer. The heat generation layer is formed of a resistance heating element and is arranged in at least one of the storage layer and the fixed layer. With this configuration, it becomes possible to provide a storage device that realizes both a high information retention property and a low power consumption.

The present technology relates to a storage device that realizes both a high information retention property and a low power consumption. A storage device includes a fixed layer, a storage layer, an intermediate layer, and a heat generation layer. The fixed layer includes a first ferromagnetic layer that includes a fixed perpendicular magnetization. The storage layer includes a second ferromagnetic layer that includes a perpendicular magnetization invertible by a spin injection. The intermediate layer is formed of an insulator and is arranged between the storage layer and the fixed layer. The heat generation layer is formed of a resistance heating element and is arranged in at least one of the storage layer and the fixed layer. With this configuration, it becomes possible to provide a storage device that realizes both a high information retention property and a low power consumption.

A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

This invention relates to structures comprising magnetic materials and conjugated molecules. The invention relates to magneto-resistive devices based on such structures. Structures and devices of the invention can be used as magnetic switches, magnetic sensors and in devices such in/as memory devices.