A magnetic recording array includes a plurality of spin elements arranged in a matrix, each spin element including a wiring and a stacked body that includes a first ferromagnetic layer stacked on the wiring, a plurality of write wirings connected to first ends of the respective wirings in the plurality of spin elements, a plurality of read wirings connected to the respective stacked bodies in the plurality of spin elements, and a plurality of common wirings connected to second ends of the wirings in the respective spin elements belonging to the same row, wherein the common wiring has an electrical resistance lower than the electrical resistance of the write wiring or the read wiring.

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.

A semiconductor device includes first and second contact plugs in an insulating layer that is on a substrate, the first and second contact plugs spaced apart from each other. A spin-orbit torque (SOT) line on the insulating layer and overlapping the first and second contact plug is provided. A magnetic tunnel junction (MTJ) is on the SOT line. An upper electrode is on the MTJ. Each of the first and second contact plugs includes a recess region adjacent the SOT line. A sidewall of the recess region is substantially coplanar with a side surface of the SOT line and a side surface of the MTJ.

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.

The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a topological insulator (TI) modulation layer. The TI modulation layer comprises a plurality of bismuth or bismuth-rich composition modulation layers, a plurality of TI lamellae layers comprising BiSb having a (012) crystal orientation, and a plurality of texturing layers. The TI lamellae layers comprise dopants or clusters of atoms, the clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material. The clusters of atoms are configured to have a grain boundary glass forming temperature of less than about 400° C. Doping the TI lamellae layers comprising BiSb having a (012) crystal orientation with clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material enable the SOT MTJ device to operate at higher temperatures while inhibiting migration of Sb from the BiSb of the TI lamellae layers.

According to one embodiment, a magnetic device includes first and second conductive portions, first and second stacked bodies, and a controller. The first conductive portion includes first to third region. The third region is between the first and second regions. The first stacked body includes first and second magnetic layers. The second magnetic layer is between the third region and the first magnetic layer. The second conductive portion includes fourth to sixth regions. The sixth region is between the fourth and fifth regions. The second stacked body includes third and fourth magnetic layers. The fourth magnetic layer is between the sixth region and the third magnetic layer. The first stacked body is configured to be in a first low or high electrical resistance state. The second stacked body is configured to be in a second low high electrical resistance state.

According to one embodiment, a method, computer system, and computer program product for generating true random numbers is provided. The present invention may include applying an electrical current to an entirely on-chip magnetic tunnel junction (MTJ) to cause the MTJ to oscillate between a high resistance state and a low resistance state; responsive to removing the electrical current and allowing the MTJ to randomly relax into the high resistance state or the low resistance state, reading the resistance state of the MTJ.