A magnetic memory device includes a first magnetic memory cell extending in a first direction and including a first magnetic domain and a second magnetic domain arranged in the first direction, and a second magnetic memory cell extending in the first direction and including a third magnetic domain and a fourth magnetic domain arranged in the first direction. A magnetization direction of the first magnetic domain and a magnetization direction of the second magnetic domain are anti-parallel to each other. A magnetization direction of the third magnetic domain and a magnetization direction of the fourth magnetic domain are anti-parallel to each other. The third magnetic domain of the second magnetic memory cell is spaced apart from the second magnetic domain of the first magnetic memory cell in a second direction intersecting the first direction.

A magnetic memory according to en embodiment includes: a first and second wirings; an insulator portion; a magnetic member including: a first portion electrically connected to the first wiring; a second portion electrically connected to the second wiring; and a third portion disposed between the first and second portions, the magnetic member extending in a first direction from the first portion toward the second portion and surrounding the insulator portion, and in a cross-section parallel to the first direction and including part of the magnetic member and part of the insulator portion, a curvature of the first portion being smaller than a curvature of the third portion, a length of the first portion in the first direction being greater than half a length of the third portion in the first direction; and a control circuit electrically connected to the first and second wirings.

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.

A magnetoresistance effect element includes: a laminate in which a first ferromagnetic layer, a non-magnetic layer, and a second ferromagnetic layer are laminated in order in a first direction; a magnetic body that is present on the second ferromagnetic layer or above the second ferromagnetic layer of the laminate; and a wiring that is in contact with a first side surface of the magnetic body and extends in a second direction crossing the first direction. The thickness of the second ferromagnetic layer in the first direction is thinner than the minimum length of the second ferromagnetic layer in a plane orthogonal to the first direction. The thickness of the magnetic body in the first direction is thicker than the minimum length of the magnetic body in a plane orthogonal to the first direction.

Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.

According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.