In general, according to one embodiment, a magnetoresistance memory device comprising includes: a layer stack including a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; a first nitride on a side surface of the layer stack; a first layer on a side surface of the first nitride; a second layer on a side surface of the first layer, a first electrode on the layer stack; and a second nitride on a side surface of the second layer. The second layer is in contact with the first layer at a position above an upper surface of the first layer.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.

A magnetic memory according to an embodiment includes: a first wiring; a second wiring; a first switching element disposed between the first wiring and the second wiring; a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring; a third wiring disposed between the first magnetic member and the second wiring; a first magnetoresistive element disposed between the third wiring and the second wiring; and a second switching element disposed between the first magnetoresistive element and the second wiring.

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

According to one embodiment, a storage device includes a magnetoresistive effect element comprising a nonmagnetic layer and a stacked body on the nonmagnetic layer. The stacked body includes a first ferromagnetic layer on the nonmagnetic layer, a second ferromagnetic layer exchange-coupled with the first ferromagnetic layer, and a magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The magnetic layer includes a magnetic material and at least one compound selected from among a carbide, a nitride, and a boride.

Provided is a spin current magnetization rotational element, including: a first ferromagnetic metal layer for a magnetization direction to be changed; and a spin-orbit torque wiring which extends in a second direction intersecting a first direction that is a plane-orthogonal direction of the first ferromagnetic metal layer, the first ferromagnetic metal layer being located on one surface of the spin-orbit torque wiring, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer and an interfacial spin generation layer are alternately laminated in the first direction, a number of a plurality of the interfacial spin generation layers is two or more, and at least one of the plurality of the interfacial spin generation layer is made of a compound.

According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.

A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.

A magnetic memory according to an embodiment includes: a first wiring; a second wiring; a first switching element disposed between the first wiring and the second wiring; a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring; a third wiring disposed between the first magnetic member and the second wiring; a first magnetoresistive element disposed between the third wiring and the second wiring; and a second switching element disposed between the first magnetoresistive element and the second wiring.