A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.

Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

An ionic transistor including a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ionic transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ionic transistor further includes an electrolyte layer situated between and electrically connected to the first and second storage layers. The ionic transistor may be implemented as non-volatile memory in a machine learning (ML) application.

Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.

The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.

A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.