Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.

An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Disclosed are a neuromorphic device and a unit synapse devices forming the same. The unit synapse device has a learning device and an inference device. The learning device and the inference device may share a via oxide layer and a common electrode, and a learning operation and an inference operation may be performed in one unit synapse device.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

Embodiments of the present invention provide a computer system, a voltage resistance controlling apparatus, and a method that comprises at least two electrodes on proximal endpoints; a first layer disposed on the at least two electrodes, wherein the first layer is a made of a metal-oxide; a second layer disposed on the second layer, wherein the second first layer is made of an electrically conductive metal-oxide; a forming contact disposed on the second layer, wherein a combination of the forming contact disposed on the first layer disposed on the second layer operatively connects the at least two electrodes; and a computer system operatively connected to the forming contact, wherein the computer system is configured to apply a predetermined voltage to the first layer and the second layer respectively and display an overall resistance increase using a user interface.

Cross-point arrays and methods of updating values of the same include input resistive processing units (RPUs), each having a settable resistance, each connected to a common node. Output RPUs each have a settable resistance and are each connected to the common node. An update switch is configured to connect an update voltage to the common node.