Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.

A neuromorphic architecture is formed from a laminate of non-woven carbon fiber reinforced polymer layers arranged in a plurality of different directions. A plurality of distributed nodes are formed through the laminate via transverse voids, and an encapsulant encapsulates an electrochemical fluid or gel such that the electrochemical fluid or gel may flow within the nodes and around the laminate. Electrical current flowing through the architecture creates reversible metal deposits at various nodes, depending on the path developed through the architecture, with a complexity sufficient for neuromorphic processing, and providing a writable and erasable memory. A neuromorphic actuator may be formed by combining shape memory materials with such a neuromorphic architecture, which may provide desired surface contours and/or actuations based on current in the neuromorphic architecture. Such neuromorphic architectures and actuators may be trained according to various methods, using feed-forward and/or feedback techniques.

A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.

The present disclosure generally relates to combinations of resistive change elements and resistive change element arrays thereof. The present disclosure also generally relates to combinational resistive change elements and combinational resistive change element arrays thereof. The present disclosure additionally generally relates to devices and methods for programming and accessing combinations of resistive change elements. The present disclosure further generally relates to devices and methods for programming and accessing combinational resistive change elements.

Combinations of resistive change elements and resistive change element arrays thereof are described. Combinational resistive change elements and combinational resistive change element arrays thereof are described. Devices and methods for programming and accessing combinations of resistive change elements are described. Devices and methods for programming and accessing combinational resistive change elements are described.

A protein memory cell and a protein memory system are provided. The protein memory cell includes: first and second electrodes disposed to be spaced apart from each other on a micro channel; a gap region defined between the first and second electrodes on the micro channel; an outer region defined as an opposite side to the gap region based on the first or second electrode on the micro channel; and a photosensitive protein changing conductivity between the first and second electrodes while moving between the gap region and the outer region depending on structural conversion of a chromophore.

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

The invention relates to a process for the production of an electronic component comprising a self-assembled monolayer (SAM) using compounds of the formula I

R.sup.1-(A.sup.1-Z.sup.1).sub.r—(B.sup.1).sub.n—(Z.sup.2-A.sup.2).sub.s-Sp-G   (I)

in which the groups occurring have the meanings defined in claim 1; the present invention furthermore relates to the use of the components in electronic switching elements and to compounds for the production of the SAM.

Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.