A selective non-volatile memory device includes a first electrode, a second electrode and at least one layer made of an active material. The device has at least two programmable memory states associated with two voltage thresholds and also provides a selective role when it is in a highly resistive state.

The present invention relates to a neuromorphic circuit suitable for implementing a neural network, the neuromorphic circuit comprising: lines of words, pairs of complementary bit-lines, source lines, a set of elementary cells, an electronic circuit implementing a neurone having an output and including: a set of logic components, a counting unit, a comparison unit comprising a comparator and a comparison voltage generator, the comparator being suitable for comparing the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit which implements a neurone.

A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.

The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven. When the first current-applying block is selected, a second voltage is applied to the second electrode. When the second current-applying block is selected, the second voltage is applied to the first electrode. The first voltage has a voltage level by a threshold voltage higher than the second voltage.

Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.

In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a variable resistance memory cell of the array to change a threshold voltage of the variable resistance memory cell in an analog fashion from a voltage associated with a reset state to effectuate a first synaptic weight change; and apply additional sub-threshold voltage pulses to the variable resistance memory cell to effectuate each subsequent synaptic weight change.

An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

A memory unit with a multiply-accumulate assist scheme for a plurality of multi-bit convolutional neural network based computing-in-memory applications is controlled by a reference voltage, a word line and a multi-bit input voltage. The memory unit includes a non-volatile memory cell, a voltage divider and a voltage keeper. The non-volatile memory cell is controlled by the word line and stores a weight. The voltage divider includes a data line and generates a charge current on the data line according to the reference voltage, and a voltage level of the data line is generated by the non-volatile memory cell and the charge current. The voltage keeper generates an output current on an output node according to the multi-bit input voltage and the voltage level of the data line, and the output current is corresponding to the multi-bit input voltage multiplied by the weight.