A memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. The control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (RC) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.