A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed.

An operating method of a semiconductor device including a controller and a non-volatile memory device operating under control of the controller is provided. The operating method includes determining, by the controller, whether the non-volatile memory device satisfies a block program condition; based on the non-volatile memory device satisfying the block program condition, performing a block program operation a plurality of times; and based the non-volatile memory device not satisfying the block program condition, performing an erase operation.

Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

A memory device configured to perform a program operation and a backup operation together includes a memory block including a main sub block including selected memory cells in which program data is programmed among a plurality of memory cells respectively connected to a plurality of word lines, and a backup block in which page data included in the program data is backed up, a peripheral circuit configured to perform a plurality of program loops to program the program data in the selected memory cells, and control logic configured to control the peripheral circuit to back up any one of the page data while programming the selected memory cells in preset program loops among the plurality of program loops.

Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.

An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.