Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.

A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

A shift register unit, includes: a first output module and a second output module, configured to output a signal of a clock signal terminal to a signal output terminal under the control of a pull-up control node; an input module, configured to output a voltage of the first power supply terminal to the pull-up control node under the control of a signal of the signal input terminal; a pull-down control module, configured to pull down a signal of the pull-down control node to a voltage of the second power supply terminal under the control of the signal input terminal; a pull-down module, configured to pull down signals of the pull-up control node and the signal output terminal to the voltage of the second power supply under the control of the pull-down control node; and a reset module, configured to output a signal of the first power supply terminal to the pull-down control node under the control of the reset signal terminal. The shift register unit is capable of raising the output capability of the signal output terminal and shortening the falling time of the output waveform. A gate driving circuit and a display apparatus are also provided.

A shift register unit and a method for driving the shift register unit, a gate drive circuit and a display device are provided. The shift register unit includes an inputting unit, an outputting unit, a reset unit, a first control unit and a second control unit, a first node, a second node, a third node, a shift signal outputting terminal and multiple inputting terminals. A width of a shift pulse output by the shift register unit may be adjusted by adjusting a width of a shift pulse input to the shift register unit, and the output shift pulse and the input shift pulse have an identical width.

A gate on array (GOA) unit, a gate driver circuit, and a display device are provided. The GOA unit includes a driver circuit configured to output a first clock signal from an output end of the GOA unit. The GOA unit further includes a pull-down circuit connected with the driver circuit, the pull-down circuit also connected with at least one low-voltage end that provides a low-voltage signal, the pull-down circuit configured to input the low-voltage signal into a control end of the driver circuit to drive the driver circuit to be in an off state when the GOA unit outputs an off signal. The GOA unit can avoid incorrect switching-on of one row of pixels corresponding to the GOA unit, so that the row of pixels cannot be charged and display incorrect images, and hence an “abnormal image” phenomenon can be overcome.

A display panel includes a substrate, and a pixel array and a gate driving circuit. The gate driving circuit provides gate driving signals to the pixel array, and includes shift registers, wherein each shift register includes a voltage providing unit, a first driving transistor, a voltage transmitting unit and a second driving transistor. The voltage providing unit receives a setting signal and a system high voltage to provide a first terminal voltage. The first driving transistor receives a first clock signal and the first terminal voltage to provide a first gate driving signal. The voltage transmitting unit receives the first gate driving signal to provide a second terminal voltage. The second driving transistor receives a second clock signal and the second terminal voltage to provide a second gate driving signal. Therefore, the influence caused by large difference of driving capabilities of the first and the second driving transistor is avoided.

A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Provided are a gate line driving circuit, a circuit for outputting an emission control signal, and a display device, the problem that existing gate line driving circuit can output a synchronous driving signal is solved. The gate line driving circuit comprises a power input pin configured to input an effective voltage (VGH) for controlling a switching transistor in a pixel region to be turned off, the power input pin inputs the effective voltage (VGH) in a display phase, and inputs a synchronous driving signal in a touch phase.

The embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device. The shift register unit, comprises two transfer gate modules (211, 212), four AND gate modules (231, 232, 233, 234), and two capacitor modules (241, 242), as well as a pulse signal input terminal (IN), four pulse signal output terminals (L1, L2, L3, L4), and a plurality of clock signal input terminals (CLK1 to CLK8). The shift register unit provided in the present disclosure can make the layout area occupied by the corresponding gate driving circuit reduce greatly as compared with that occupied by the gate driving circuit in the prior art, which facilitates border narrowing of the corresponding display device.