A display panel, a shift register circuit, and a driving method of the shift register circuit are provided. The shift register circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. When turned on individually, the first transistor provides an input signal to a second node, the second transistor provides the input signal to the first node, the third transistor provides a charging signal to a second node, the fourth transistor provides a first voltage signal to a third node, the fifth transistor provides a voltage signal at the third node to the first node, the sixth transistor provides the first voltage signal to a signal output terminal, and the seventh transistor provides the second clock signal to the signal output terminal.

A display driver is configured to drive a display device according to a video signal. The display signal includes a plurality of first to N-th output amplifiers (N is an integer greater than two) and an output electrical current capacity setting portion. The first to N-th output amplifiers are configured to amplify first to N-th gradation voltages a representing brightness level per pixel according to the video signal, so that the first to N-th output amplifiers obtain first to N-th pixel drive voltages. Further, the first to N-th output amplifiers are configured to output the first to N-th pixel drive voltages to the display device. The output electrical current capacity setting portion is configured to set an output electrical current capacity of each of the first to N-th output amplifiers individually or in a group of a plurality of output amplifiers.

The present invention discloses a shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, and comprising first to third P-type transistors, and gates of the first, second P-type transistors respectively receive gate voltages of n−2th, n−2th pixels, and first end of the first, second P-type transistors respectively receive first and second input signals, and both second ends of the first and second P-type transistors are coupled to a gate of the third P-type transistor; the gate voltages of the n−2th, n−2th pixels are respectively employed to control on-off of the first and second P-type transistors, and to make the first input signal on-off the third P-type transistor; n is a nature number larger than 2; a first end of the third P-type transistor is coupled to a first clock signal or a second clock signal, and a second end is employed as being a voltage output end to be coupled to the nth pixel. The present invention can diminish the dimension of the frame of liquid crystal display. The present invention also provides a gate driving circuit and a liquid crystal display.

A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.

The present application discloses a shift-register circuit configured as one of a plurality of shift-register units cascaded in series. The shift-register circuit includes a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port. The pull-up sub-circuit is configured to pass a first clock signal from the first clock port to the output port when the pull-up node is set to a turn-on voltage. Additionally, the shift-register circuit includes a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port. The chamfering sub-circuit is configured to pass a chamfering clock signal from the chamfering clock port to the output port. The chamfering clock signal is at the turn-on voltage simultaneously with the first clock signal and becomes a turn-off voltage slightly earlier in time than the first clock signal.

The present invention provides a Gate driver on Array circuit, a display panel and a display device. The Gate driver on Array circuit comprises: shift register SR circuits of multiple stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; and the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch panel scan signal, and a S electrode of the switch is coupled to a K output end, and a D electrode of the switch is coupled to a scan line gate electrode signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP signal.

A shift register, a drive method, a drive circuit, a display substrate, and a display device are provided. The shift register includes an input unit, a first control unit, a second control unit, an output unit, and a voltage stabilizing unit. The input unit is configured to provide a signal of a signal input end to a first node and a signal of a first power supply end to a second node. The first control unit is configured to control a signal of a fourth node. The second control unit is configured to provide a signal of a second power supply end to the first node. The output unit is configured to provide the signal of the first or the second power supply end to the output end. The voltage stabilizing unit is connected to the first node, fifth node, the output end, and the first power supply end.

The present invention provides a voltage output device, which comprises a direct-current power supply, a reference level input terminal, a predetermined level output terminal, a voltage regulation module and a control signal generation module, the control signal generation module comprises a control signal generation unit, the voltage regulation module comprises a plurality of storage capacitors, wherein the control signal generation unit can send a charging control signal to the voltage regulation module in a charging stage of the voltage output device, and send an operation control signal to the voltage regulation module in an operating stage of the voltage output device. The present invention further provides a gate driving circuit and a display apparatus. With the voltage output device provided by the present invention, a high-level voltage that is high enough and/or a low-level voltage that is low enough can be outputted, thereby satisfying specific application requirements.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

The present disclosure discloses a shift register unit, a gate drive circuit, and a display device. The shift register unit includes first to twelfth switch elements, a first capacitor, and a second capacitor. The first switch element switches on in response to an input signal, the second switch element switches on in response to a first clock signal, the third, the ninth and the twelfth switch elements switch on in response to a signal of the second node, the fourth switch element switches on in response to a signal of the first node, and the fifth, the seventh and the eleventh switch elements switch on in response to a second clock signal.