Wafer-level testing of multiple adjacent semiconductor die of a semiconductor wafer in parallel using built-in self-test circuitry for a memory (mBIST) and scribe lines that connect certain terminals of a semiconductor die to terminals of an adjacent semiconductor die. During the wafer-level testing, probe needles of a test setup connect to a single one of the multiple adjacent semiconductor die, and mBIST commands are passed from the single one of the multiple adjacent semiconductor die to one or more adjacent semiconductor die. In some examples, the scribe lines connect mBIST circuit terminals of one semiconductor die to mBIST circuit terminals of an adjacent semiconductor die. In some examples, the scribe lines connect I/O terminals of one semiconductor die to I/O terminals of an adjacent semiconductor die. The scribe lines may cross scribe regions of the wafer to connect the respective terminals of the adjacent semiconductor die.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.

An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.

In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.