A memory includes a storage circuit, a first reading circuit, a second reading circuit, and a plurality of correcting circuits. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays. The sense amplifier arrays and the storage unit arrays are arranged alternately, and the sense amplifier arrays are configured to perform data reading and writing on the storage unit arrays. The first reading circuit is configured to compare a reference voltage signal with a signal on a first data line corresponding to the first reading circuit, and output a comparison result as read-out data. The second reading circuit is configured to compare the reference voltage signal with a signal on a first data line corresponding to the second reading circuit, and output a comparison result as read-out data.

A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device then adjusts a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before the second programming pass of the programming operation is performed on the memory cell.

A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.

Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

A test apparatus configured to test a device under test includes a power supply and a power compensation circuit. The power supply is configured to supply electric power to a power supply terminal of the device under test via a first route or a second route that are connected in parallel. The first route includes a first switch element configured to be controlled according to a first control signal. The power compensation circuit is located on the second route, wherein the power compensation circuit includes a second switch element configured to be controlled according to a second control signal, the power compensation circuit is configured to generate a compensation pulse current when the first switch element is turned off and the second switch element is turned on.

A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.