A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V.sub.dd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V.sub.th) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V.sub.ss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

A three-dimensional (3D) memory device includes a memory cell array formed by a plurality of memory cells, the memory cells in a same row are connected to a same word line; a word line driving circuit including a driving voltage source for providing a driving voltage to a selected word line; at least one word line leakage detection circuit, configured to detect a leakage state of the selected word line; and at least one coupling circuit corresponding to the word line leakage detection circuit. The coupling circuit includes a switch and an isolation capacitor arranged between the switch and the word line leakage detection circuit, and the isolation capacitor is used for isolating the word line leakage detection circuit and the word line driving circuit.

Methods, systems, and devices supporting an auto-power on mode for biased testing of a power management integrated circuit (PMIC) are described. A system may program a PMIC of a memory system to a specific mode. The mode may cause the PMIC to apply a bias to a memory device of the memory system upon receiving power and independent of a command to apply the bias to the memory device. The system may transmit power to the memory system while controlling one or more operating conditions (e.g., temperature, humidity) for a threshold time. The PMIC may apply a bias to the memory device during the threshold time based on the PMIC being programmed to the mode and the transmitted power. The system may identify a capability or defect of the memory device resulting from transmitting the power to the memory system while controlling the operating conditions for the threshold time.

A corresponding value of a data state metric associated with each of a value of a plurality of values of a memory access operation parameter used in one or more memory access operation is measured. An optimal metric value based on the measured values of the predetermined data state metric is determined. An optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter is selected.

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.

A method for testing a memory and a memory testing device are provided. The method for testing the memory includes writing data to a memory including a candidate storage unit, a fuse, and a redundant unit for replacing the candidate storage unit through the fuse when the candidate storage unit is determined to be defective; adjusting a temperature of the memory, and while adjusting the temperature, repeatedly refreshing the memory and recording the state of the fuse; reading the data of the memory if the temperature of the memory is stable at a predetermined temperature; and determining that the fuse is defective if the read data of the memory has an error.