Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.

A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.

A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.

A deterioration detection device includes a storage including a first current path and a second current path and configured such that a current is applied to the first current path and the second current path, a storage input control unit configured to compare an internal operating condition of a memory device with a target condition in a first operating mode and to select one of the first current path and the second current path of the storage based on a result of the comparison, and an output unit configured to output an output signal indicated deterioration, accumulated in one of the first current path and the second current path, in a second operating mode.

A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of semiconductor memories, and a controller for controlling the memory device to perform a test program operation and a threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation. The controller sets operation performance parameters of each of the semiconductor memories based on monitoring information obtained as a result of the threshold voltage distribution monitoring operation.

An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.