Disclosed is an operating method of an electronic device, which includes receiving input data, selecting a program voltage pattern corresponding to the input data from among a plurality of program voltage patterns for storing the input data in a memristor array circuit, and storing the input data in the memristor array circuit depending on the program voltage pattern thus selected. Each of the plurality of program voltage patterns includes a plurality of voltage pulses in which a pulse magnitude gradually increases over time.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.

A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller part transmits the signal including write data on the basis of a configured parameter, a receiver included in the data storage part receives the signal, and the write data included in the signal is written into a first storage area. The controller part reads the write data from the first storage area, determines whether or not a bit error exists in the write data, changes the parameter when the bit error exists to repeat similar determination and find an appropriate parameter at which the bit error no longer exists.

Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.

Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.