Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

A system and method for measuring the degradation of one or more memory devices of a memory sub-system. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: testing different values for a setting of the memory device, wherein the setting of the memory device affects a duty cycle of a signal internal to the memory device; selecting an optimum value for the setting based on access errors during the testing, wherein the optimum value minimizes access errors; determining a degradation measurement for the memory device based on the optimum value; and providing a notification to a host system based on the degradation measurement.

Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.

A pseudo-static random access memory is provided herein, which may improve the speed of data transmission. After a first delay from a command and a row address being input in a first operation, the pseudo-static random access memory inputs or outputs the data in the memory cells corresponding to the input row address and the input column address, which includes a control unit controlling a delay in the second operation less than the initial delay when a specific condition is satisfied. The second operation is executed after the first operation.

Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times

A memory controller includes a clock delay generator, a set of flip-flops, and a control circuit, and is connected to a processor and a memory. The clock delay generator receives a clock signal from the processor, delays the clock signal by a set of delay time intervals, and generates a set of delayed clock signals. The flip-flops receive a test pattern and read data from the memory, sample the test pattern and the read data based on the delayed clock signals, and generate a set of sampled test patterns and a set of sampled read data. The control circuit identifies a sampled test pattern that is equal to the test pattern and the corresponding delayed clock signal as a read clock signal, and outputs the sampled read data that corresponds to the (delayed) read clock signal.